bus_write_1
bus_write_1((_sc)->alc_res[0], (reg), (val))
bus_write_1((_sc)->ale_res[0], (reg), (val))
bus_write_1((sc)->mem[0], (reg), (val))
#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
bus_write_1((sc)->msk_res[0], (reg), (val))
bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
#define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val)
bus_write_1((sc)->sk_res[0], (reg), (val))
#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val)
bus_write_1(sc->vge_res, reg, val)
#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->port_res, reg, val)
#define CSR_MEM_WRITE_1(sc, reg, val) bus_write_1(sc->mem_res, reg, val)
bus_write_1(sc->mem_aux_res, reg, val)