headers/cpp/std/gslice_array.h

156

_DEFINE_VALARRAY_OPERATOR(&, and)

headers/cpp/std/indirect_array.h

144

_DEFINE_VALARRAY_OPERATOR(&, and)

headers/cpp/std/mask_array.h

141

_DEFINE_VALARRAY_OPERATOR(&, and)

headers/cpp/std/slice_array.h

143

_DEFINE_VALARRAY_OPERATOR(&, and)

headers/cpp/std/std_valarray.h

615

_DEFINE_VALARRAY_AUGMENTED_ASSIGNMENT(&, and)

headers/cpp/std/std_valarray.h

638

_DEFINE_VALARRAY_EXPR_AUGMENTED_ASSIGNMENT(&, and)

headers/cpp/std/valarray_array.h

329

_DEFINE_ARRAY_FUNCTION(&, and)

src/add-ons/accelerants/intel_extreme/mode.cpp

443

8. Configure and enable CPU planes (VGA or hires)

src/add-ons/accelerants/intel_extreme/mode.cpp

448

ii. Enable CPU FDI Transmitter and PCH FDI Receiver with Training Pattern 1 enabled.

src/add-ons/accelerants/intel_extreme/mode.cpp

451

v. Enable training pattern 2 on CPU FDI Transmitter and PCH FDI Receiver

src/add-ons/accelerants/intel_extreme/mode.cpp

455

viii. Enable normal pixel output on CPU FDI Transmitter and PCH FDI Receiver

src/add-ons/accelerants/intel_extreme/mode.cpp

457

c. Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling

src/add-ons/accelerants/intel_extreme/mode.cpp

459

d. [DevCPT] Configure DPLL SEL to set the DPLL to transcoder mapping and enable DPLL to the

src/add-ons/accelerants/intel_extreme/mode.cpp

462

f. Configure PCH transcoder timings, M/N/TU, and other transcoder settings (should match CPU settings).

src/add-ons/accelerants/intel_extreme/mode.cpp

463

g. [DevCPT] Configure and enable Transcoder DisplayPort Control if DisplayPort will be used