__SHIFTOUT
#define __SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask))
ofs = __SHIFTOUT(iv_ofs, BWI_FW_IV_OFS_MASK);
if (__SHIFTOUT(val, BWI_STATE_HI_FLAGS_MASK) &
phyrev = __SHIFTOUT(val, BWI_PHYINFO_REV_MASK);
phytype = __SHIFTOUT(val, BWI_PHYINFO_TYPE_MASK);
phyver = __SHIFTOUT(val, BWI_PHYINFO_VER_MASK);
idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);
rf->rf_txpower_max = __SHIFTOUT(val,
rf->rf_txpower_max = __SHIFTOUT(val,
ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);
ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);
rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);
val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);
tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);
tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);
lna_gain = __SHIFTOUT(le16toh(hdr->rxh_phyinfo),
manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);
type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);
rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);
src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
data_txcnt = __SHIFTOUT(stats->txs_txcnt,
tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
data_txcnt = __SHIFTOUT(tx_status0,
busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
__SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT);
OS_ASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6);
exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG);
exit->exitstate.cr8 = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR);
seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE);
seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S);
seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL);
seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P);
seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL);
seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L);
seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF);
seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G);
state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v,
if (__SHIFTOUT(descs.eax, CPUID_8_0A_EAX_SvmRev) != 1) {
if (__SHIFTOUT(qual, INTR_INFO_TYPE) != INTR_TYPE_NMI) {
clevel = __SHIFTOUT(cpudata->gprs[NVMM_X64_GPR_RAX],
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
switch (__SHIFTOUT(qual, VMX_QUAL_CR_NUM)) {
exit->u.io.port = __SHIFTOUT(qual, VMX_QUAL_IO_PORT);
OS_ASSERT(__SHIFTOUT(info, VMX_INFO_IO_SEG) < 6);
exit->u.io.seg = __SHIFTOUT(info, VMX_INFO_IO_SEG);
if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_64) {
} else if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_32) {
} else if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_16) {
if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_32) {
} else if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_16) {
} else if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_8) {
switch (__SHIFTOUT(info, INTR_INFO_TYPE)) {
segs[idx].attrib.type = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_TYPE);
segs[idx].attrib.s = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_S);
segs[idx].attrib.dpl = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_DPL);
segs[idx].attrib.p = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_P);
segs[idx].attrib.avl = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_AVL);
segs[idx].attrib.l = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_L);
segs[idx].attrib.def = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_DEF);
segs[idx].attrib.g = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_G);
if (__SHIFTOUT(msr, IA32_VMX_BASIC_MEM_TYPE) != MEM_TYPE_WB) {
exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT);
OS_ASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6);
exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG);
exit->exitstate.cr8 = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR);
seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE);
seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S);
seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL);
seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P);
seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL);
seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L);
seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF);
seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G);
state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v,
if (__SHIFTOUT(descs.eax, CPUID_8_0A_EAX_SvmRev) != 1) {
if (__SHIFTOUT(qual, INTR_INFO_TYPE) != INTR_TYPE_NMI) {
clevel = __SHIFTOUT(cpudata->gprs[NVMM_X64_GPR_RAX],
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);
gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
switch (__SHIFTOUT(qual, VMX_QUAL_CR_NUM)) {
exit->u.io.port = __SHIFTOUT(qual, VMX_QUAL_IO_PORT);
OS_ASSERT(__SHIFTOUT(info, VMX_INFO_IO_SEG) < 6);
exit->u.io.seg = __SHIFTOUT(info, VMX_INFO_IO_SEG);
if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_64) {
} else if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_32) {
} else if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_16) {
if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_32) {
} else if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_16) {
} else if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_8) {
switch (__SHIFTOUT(info, INTR_INFO_TYPE)) {
segs[idx].attrib.type = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_TYPE);
segs[idx].attrib.s = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_S);
segs[idx].attrib.dpl = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_DPL);
segs[idx].attrib.p = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_P);
segs[idx].attrib.avl = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_AVL);
segs[idx].attrib.l = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_L);
segs[idx].attrib.def = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_DEF);
segs[idx].attrib.g = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_G);
if (__SHIFTOUT(msr, IA32_VMX_BASIC_MEM_TYPE) != MEM_TYPE_WB) {
val = __SHIFTOUT(val, instr->src.u.reg->mask);
val = __SHIFTOUT(val, instr->dst.u.reg->mask);