__SHIFTIN
__SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
__SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
state_lo &= ~__SHIFTIN(BWI_STATE_LO_FLAG_PHYRST,
__SHIFTIN(tpctl->tp_ctrl1, BWI_RFR_TXPWR1_MASK));
__SHIFTIN(bbp_atten, mask));
__SHIFTIN(bbp_atten, mask));
thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |
__SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);
val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
__SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);
val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
__SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
__SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
__SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
__SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
__SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
__SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
__SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
__SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
__SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
__SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
__SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
__SHIFTIN(ncpus - 1, CPUID_8_08_ECX_NC) |
__SHIFTIN(ilog2(NVMM_MAX_VCPUS), CPUID_8_08_ECX_ApicIdSize);
__SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) |
__SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) |
__SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) |
__SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) |
__SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) |
__SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) |
__SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) |
__SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G);
vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8],
__SHIFTIN((uint64_t)vector, VMCB_CTRL_EVENTINJ_VECTOR) |
__SHIFTIN((uint64_t)type, VMCB_CTRL_EVENTINJ_TYPE) |
__SHIFTIN((uint64_t)err, VMCB_CTRL_EVENTINJ_EV) |
__SHIFTIN((uint64_t)1, VMCB_CTRL_EVENTINJ_V) |
__SHIFTIN((uint64_t)error, VMCB_CTRL_EVENTINJ_ERRORCODE);
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(ncpus,
__SHIFTIN((uint64_t)vector, INTR_INFO_VECTOR) |
__SHIFTIN((uint64_t)type, INTR_INFO_TYPE) |
__SHIFTIN((uint64_t)err, INTR_INFO_ERROR) |
__SHIFTIN((uint64_t)1, INTR_INFO_VALID);
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(ncpus,
__SHIFTIN(ncpus - 1, CPUID_0_04_EAX_SHARING);
__SHIFTIN(0, CPUID_0_04_EAX_SHARING);
__SHIFTIN(ncpus - 1, CPUID_0_04_EAX_CORE_P_PKG);
__SHIFTIN(ecx, CPUID_0_0B_ECX_LVLNUM) |
__SHIFTIN(CPUID_0_0B_ECX_LVLTYPE_SMT, CPUID_0_0B_ECX_LVLTYPE);
__SHIFTIN(ecx, CPUID_0_0B_ECX_LVLNUM) |
__SHIFTIN(CPUID_0_0B_ECX_LVLTYPE_CORE, CPUID_0_0B_ECX_LVLTYPE);
__SHIFTIN(segs[idx].attrib.type, VMX_SEG_ATTRIB_TYPE) |
__SHIFTIN(segs[idx].attrib.s, VMX_SEG_ATTRIB_S) |
__SHIFTIN(segs[idx].attrib.dpl, VMX_SEG_ATTRIB_DPL) |
__SHIFTIN(segs[idx].attrib.p, VMX_SEG_ATTRIB_P) |
__SHIFTIN(segs[idx].attrib.avl, VMX_SEG_ATTRIB_AVL) |
__SHIFTIN(segs[idx].attrib.l, VMX_SEG_ATTRIB_L) |
__SHIFTIN(segs[idx].attrib.def, VMX_SEG_ATTRIB_DEF) |
__SHIFTIN(segs[idx].attrib.g, VMX_SEG_ATTRIB_G) |
vmcs->ident = __SHIFTIN(rev, VMCS_IDENT_REVISION);
__SHIFTIN(vmx_eptp_type, EPTP_TYPE) |
__SHIFTIN(4-1, EPTP_WALKLEN) |
vmxon->ident = __SHIFTIN(revision, VMXON_IDENT_REVISION);
__SHIFTIN(ncpus - 1, CPUID_8_08_ECX_NC) |
__SHIFTIN(ilog2(NVMM_MAX_VCPUS), CPUID_8_08_ECX_ApicIdSize);
__SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) |
__SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) |
__SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) |
__SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) |
__SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) |
__SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) |
__SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) |
__SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G);
vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8],
__SHIFTIN((uint64_t)vector, VMCB_CTRL_EVENTINJ_VECTOR) |
__SHIFTIN((uint64_t)type, VMCB_CTRL_EVENTINJ_TYPE) |
__SHIFTIN((uint64_t)err, VMCB_CTRL_EVENTINJ_EV) |
__SHIFTIN((uint64_t)1, VMCB_CTRL_EVENTINJ_V) |
__SHIFTIN((uint64_t)error, VMCB_CTRL_EVENTINJ_ERRORCODE);
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(ncpus,
__SHIFTIN((uint64_t)vector, INTR_INFO_VECTOR) |
__SHIFTIN((uint64_t)type, INTR_INFO_TYPE) |
__SHIFTIN((uint64_t)err, INTR_INFO_ERROR) |
__SHIFTIN((uint64_t)1, INTR_INFO_VALID);
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,
cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(ncpus,
__SHIFTIN(ncpus - 1, CPUID_0_04_EAX_SHARING);
__SHIFTIN(0, CPUID_0_04_EAX_SHARING);
__SHIFTIN(ncpus - 1, CPUID_0_04_EAX_CORE_P_PKG);
__SHIFTIN(ecx, CPUID_0_0B_ECX_LVLNUM) |
__SHIFTIN(CPUID_0_0B_ECX_LVLTYPE_SMT, CPUID_0_0B_ECX_LVLTYPE);
__SHIFTIN(ecx, CPUID_0_0B_ECX_LVLNUM) |
__SHIFTIN(CPUID_0_0B_ECX_LVLTYPE_CORE, CPUID_0_0B_ECX_LVLTYPE);
__SHIFTIN(segs[idx].attrib.type, VMX_SEG_ATTRIB_TYPE) |
__SHIFTIN(segs[idx].attrib.s, VMX_SEG_ATTRIB_S) |
__SHIFTIN(segs[idx].attrib.dpl, VMX_SEG_ATTRIB_DPL) |
__SHIFTIN(segs[idx].attrib.p, VMX_SEG_ATTRIB_P) |
__SHIFTIN(segs[idx].attrib.avl, VMX_SEG_ATTRIB_AVL) |
__SHIFTIN(segs[idx].attrib.l, VMX_SEG_ATTRIB_L) |
__SHIFTIN(segs[idx].attrib.def, VMX_SEG_ATTRIB_DEF) |
__SHIFTIN(segs[idx].attrib.g, VMX_SEG_ATTRIB_G) |
vmcs->ident = __SHIFTIN(rev, VMCS_IDENT_REVISION);
__SHIFTIN(vmx_eptp_type, EPTP_TYPE) |
__SHIFTIN(4-1, EPTP_WALKLEN) |
vmxon->ident = __SHIFTIN(revision, VMXON_IDENT_REVISION);
val = __SHIFTIN(val, instr->dst.u.reg->mask);
val = __SHIFTIN(val, instr->src.u.reg->mask);