__BITS
uint16_t mask = __BITS(3, 0);
#define NRSSI_11G_MASK __BITS(13, 8)
#define NRSSI_THR1_MASK __BITS(5, 0)
#define NRSSI_THR2_MASK __BITS(11, 6)
#define BWI_RFR_TXPWR1_MASK __BITS(6, 4)
#define BWI_RFR_BBP_ATTEN_CALIB_IDX __BITS(4, 1)
#define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
#define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
#define BWI_CLOCK_CTRL_CLKSRC __BITS(2, 0)
#define BWI_CLOCK_CTRL_FDIV __BITS(31, 16) /* freq divisor */
#define BWI_CLOCK_INFO_FDIV __BITS(31, 16) /* freq divisor */
#define BWI_MAC_STATUS_GPOSEL_MASK __BITS(15, 14)
#define BWI_LO_TSSI_MASK __BITS(7, 0)
#define BWI_HI_TSSI_MASK __BITS(15, 8)
#define BWI_TXSTATUS0_FREASON_MASK __BITS(4, 2) /* Failure reason */
#define BWI_TXSTATUS0_RTS_TXCNT_MASK __BITS(11, 8)
#define BWI_TXSTATUS0_DATA_TXCNT_MASK __BITS(15, 12)
#define BWI_TXSTATUS0_TXID_MASK __BITS(31, 16)
#define BWI_TX32_STATUS_STATE_MASK __BITS(15, 12)
#define BWI_RX32_CTRL_HDRSZ_MASK __BITS(7, 1)
#define BWI_RX32_STATUS_INDEX_MASK __BITS(11, 0)
#define BWI_RX32_STATUS_STATE_MASK __BITS(15, 12)
#define BWI_TXRX32_CTRL_ADDRHI_MASK __BITS(17, 16)
#define BWI_TXRX32_RINGINFO_FUNC_MASK __BITS(31, 30)
#define BWI_TXRX32_RINGINFO_ADDR_MASK __BITS(29, 0)
#define BWI_PHYINFO_REV_MASK __BITS(3, 0)
#define BWI_PHYINFO_TYPE_MASK __BITS(11, 8)
#define BWI_PHYINFO_VER_MASK __BITS(15, 12)
#define BWI_RFINFO_MANUFACT_MASK __BITS(11, 0)
#define BWI_RFINFO_TYPE_MASK __BITS(27, 12)
#define BWI_RFINFO_REV_MASK __BITS(31, 28)
#define BWI_SPROM_CARD_INFO_LOCALE __BITS(11, 8)
#define BWI_SPROM_GPIO_0 __BITS(7, 0)
#define BWI_SPROM_GPIO_1 __BITS(15, 8)
#define BWI_SPROM_GPIO_2 __BITS(7, 0)
#define BWI_SPROM_GPIO_3 __BITS(15, 8)
#define BWI_SPROM_MAX_TXPWR_MASK_11BG __BITS(7, 0) /* XXX */
#define BWI_SPROM_MAX_TXPWR_MASK_11A __BITS(15, 8) /* XXX */
#define BWI_SPROM_IDLE_TSSI_MASK_11BG __BITS(7, 0) /* XXX */
#define BWI_SPROM_IDLE_TSSI_MASK_11A __BITS(15, 8) /* XXX */
#define BWI_SPROM_ANT_GAIN_MASK_11A __BITS(7, 0)
#define BWI_SPROM_ANT_GAIN_MASK_11BG __BITS(15, 8)
#define BWI_LED_ACT_MASK __BITS(6, 0)
#define BWI_FLAGS_INTR_MASK __BITS(5, 0)
#define BWI_TXRX_INTR_ERROR (__BIT(15) | __BIT(14) | __BITS(12, 10))
#define BWI_STATE_LO_FLAGS_MASK __BITS(29, 18)
#define BWI_STATE_HI_FLAGS_MASK __BITS(28, 16)
#define BWI_CONF_LO_SERVTO_MASK __BITS(2, 0) /* service timeout */
#define BWI_CONF_LO_REQTO_MASK __BITS(6, 4) /* request timeout */
#define BWI_ID_LO_BUSREV_MASK __BITS(31, 28)
#define BWI_ID_HI_REGWIN_VENDOR_MASK __BITS(31, 16)
#define BWI_INFO_BBPID_MASK __BITS(15, 0)
#define BWI_INFO_BBPREV_MASK __BITS(19, 16)
#define BWI_INFO_BBPPKG_MASK __BITS(23, 20)
#define BWI_INFO_NREGWIN_MASK __BITS(27, 24)
#define BWI_DESC32_A_FUNC_MASK __BITS(31, 30)
#define BWI_DESC32_A_ADDR_MASK __BITS(29, 0)
#define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0)
#define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16)
#define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14)
#define BWI_TXH_ID_RING_MASK __BITS(15, 13)
#define BWI_TXH_ID_IDX_MASK __BITS(12, 0)
#define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8)
#define BWI_TXS_TXCNT_DATA __BITS(7, 4)
#define BWI_FW_IV_OFS_MASK __BITS(14, 0)
if (__predict_false(pat[i] & ~__BITS(2,0)))
#define CPUID_0_01_EBX_BRAND_INDEX __BITS(7,0)
#define CPUID_0_01_EBX_CLFLUSH_SIZE __BITS(15,8)
#define CPUID_0_01_EBX_HTT_CORES __BITS(23,16)
#define CPUID_0_01_EBX_LOCAL_APIC_ID __BITS(31,24)
#define CPUID_0_04_EAX_CACHETYPE __BITS(4, 0)
#define CPUID_0_04_EAX_CACHELEVEL __BITS(7, 5)
#define CPUID_0_04_EAX_SHARING __BITS(25, 14)
#define CPUID_0_04_EAX_CORE_P_PKG __BITS(31, 26)
#define CPUID_0_07_ECX_MAWAU __BITS(21, 17)
#define CPUID_0_0B_EAX_SHIFTNUM __BITS(4, 0)
#define CPUID_0_0B_ECX_LVLNUM __BITS(7, 0)
#define CPUID_0_0B_ECX_LVLTYPE __BITS(15, 8)
#define CPUID_8_08_ECX_NC __BITS(7,0)
#define CPUID_8_08_ECX_ApicIdSize __BITS(15,12)
#define CPUID_8_08_ECX_PerfTscSize __BITS(17,16)
#define CPUID_8_0A_EAX_SvmRev __BITS(7,0)
#define SVM_EXIT_IO_PORT __BITS(31,16)
#define SVM_EXIT_IO_SEG __BITS(12,10)
#define SVM_SEG_ATTRIB_TYPE __BITS(3,0)
#define SVM_SEG_ATTRIB_DPL __BITS(6,5)
#define VMCB_CTRL_V_TPR __BITS(3,0)
#define VMCB_CTRL_V_INTR_PRIO __BITS(19,16)
#define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32)
#define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0)
#define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8)
#define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32)
#define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0)
#define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0)
#define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8)
#define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32)
#define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12)
#define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0)
#define VMX_QUAL_CR_NUM __BITS(3,0)
#define VMX_QUAL_CR_TYPE __BITS(5,4)
#define VMX_QUAL_CR_GPR __BITS(11,8)
#define VMX_QUAL_IO_SIZE __BITS(2,0)
#define VMX_QUAL_IO_PORT __BITS(31,16)
#define VMX_INFO_IO_ADRSIZE __BITS(9,7)
#define VMX_INFO_IO_SEG __BITS(17,15)
#define IA32_VMX_BASIC_IDENT __BITS(30,0)
#define IA32_VMX_BASIC_DATA_SIZE __BITS(44,32)
#define IA32_VMX_BASIC_MEM_TYPE __BITS(53,50)
exitcode &= __BITS(15,0);
#define VMX_SEG_ATTRIB_TYPE __BITS(3,0)
#define VMX_SEG_ATTRIB_DPL __BITS(6,5)
#define EPTP_TYPE __BITS(2,0)
#define EPTP_WALKLEN __BITS(5,3)
#define EPTP_PHYSADDR __BITS(63,12)
#define INTR_INFO_VECTOR __BITS(7,0)
#define INTR_INFO_TYPE __BITS(10,8)
#define VMXON_IDENT_REVISION __BITS(30,0)
#define VMCS_IDENT_REVISION __BITS(30,0)
if (__predict_false(pat[i] & ~__BITS(2,0)))
#define CPUID_0_01_EBX_BRAND_INDEX __BITS(7,0)
#define CPUID_0_01_EBX_CLFLUSH_SIZE __BITS(15,8)
#define CPUID_0_01_EBX_HTT_CORES __BITS(23,16)
#define CPUID_0_01_EBX_LOCAL_APIC_ID __BITS(31,24)
#define CPUID_0_04_EAX_CACHETYPE __BITS(4, 0)
#define CPUID_0_04_EAX_CACHELEVEL __BITS(7, 5)
#define CPUID_0_04_EAX_SHARING __BITS(25, 14)
#define CPUID_0_04_EAX_CORE_P_PKG __BITS(31, 26)
#define CPUID_0_07_ECX_MAWAU __BITS(21, 17)
#define CPUID_0_0B_EAX_SHIFTNUM __BITS(4, 0)
#define CPUID_0_0B_ECX_LVLNUM __BITS(7, 0)
#define CPUID_0_0B_ECX_LVLTYPE __BITS(15, 8)
#define CPUID_8_08_ECX_NC __BITS(7,0)
#define CPUID_8_08_ECX_ApicIdSize __BITS(15,12)
#define CPUID_8_08_ECX_PerfTscSize __BITS(17,16)
#define CPUID_8_0A_EAX_SvmRev __BITS(7,0)
#define SVM_EXIT_IO_PORT __BITS(31,16)
#define SVM_EXIT_IO_SEG __BITS(12,10)
#define SVM_SEG_ATTRIB_TYPE __BITS(3,0)
#define SVM_SEG_ATTRIB_DPL __BITS(6,5)
#define VMCB_CTRL_V_TPR __BITS(3,0)
#define VMCB_CTRL_V_INTR_PRIO __BITS(19,16)
#define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32)
#define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0)
#define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8)
#define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32)
#define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0)
#define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0)
#define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8)
#define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32)
#define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12)
#define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0)
#define VMX_QUAL_CR_NUM __BITS(3,0)
#define VMX_QUAL_CR_TYPE __BITS(5,4)
#define VMX_QUAL_CR_GPR __BITS(11,8)
#define VMX_QUAL_IO_SIZE __BITS(2,0)
#define VMX_QUAL_IO_PORT __BITS(31,16)
#define VMX_INFO_IO_ADRSIZE __BITS(9,7)
#define VMX_INFO_IO_SEG __BITS(17,15)
#define IA32_VMX_BASIC_IDENT __BITS(30,0)
#define IA32_VMX_BASIC_DATA_SIZE __BITS(44,32)
#define IA32_VMX_BASIC_MEM_TYPE __BITS(53,50)
exitcode &= __BITS(15,0);
#define VMX_SEG_ATTRIB_TYPE __BITS(3,0)
#define VMX_SEG_ATTRIB_DPL __BITS(6,5)
#define EPTP_TYPE __BITS(2,0)
#define EPTP_WALKLEN __BITS(5,3)
#define EPTP_PHYSADDR __BITS(63,12)
#define INTR_INFO_VECTOR __BITS(7,0)
#define INTR_INFO_TYPE __BITS(10,8)
#define VMXON_IDENT_REVISION __BITS(30,0)
#define VMCS_IDENT_REVISION __BITS(30,0)