sys/arm64/arm64/gicv5reg.h

521

#define IRS_IDR0_PA_RANGE_MASK (0xfu << IRS_IDR0_PA_RANGE_SHIFT)

sys/arm64/arm64/gicv5reg.h

522

#define IRS_IDR0_PA_RANGE_4G (0x0u << IRS_IDR0_PA_RANGE_SHIFT)

sys/arm64/arm64/gicv5reg.h

523

#define IRS_IDR0_PA_RANGE_64G (0x1u << IRS_IDR0_PA_RANGE_SHIFT)

sys/arm64/arm64/gicv5reg.h

524

#define IRS_IDR0_PA_RANGE_1T (0x2u << IRS_IDR0_PA_RANGE_SHIFT)

sys/arm64/arm64/gicv5reg.h

525

#define IRS_IDR0_PA_RANGE_4T (0x3u << IRS_IDR0_PA_RANGE_SHIFT)

sys/arm64/arm64/gicv5reg.h

526

#define IRS_IDR0_PA_RANGE_16T (0x4u << IRS_IDR0_PA_RANGE_SHIFT)

sys/arm64/arm64/gicv5reg.h

527

#define IRS_IDR0_PA_RANGE_256T (0x5u << IRS_IDR0_PA_RANGE_SHIFT)

sys/arm64/arm64/gicv5reg.h

528

#define IRS_IDR0_PA_RANGE_4P (0x6u << IRS_IDR0_PA_RANGE_SHIFT)

sys/arm64/arm64/gicv5reg.h

529

#define IRS_IDR0_PA_RANGE_64P (0x7u << IRS_IDR0_PA_RANGE_SHIFT)