sys/arm64/include/armreg.h

1021

#define ID_AA64ISAR1_EL1_ISS ISS_MSR_REG(ID_AA64ISAR1_EL1)

sys/arm64/include/armreg.h

1140

#define ID_AA64ISAR2_EL1_ISS ISS_MSR_REG(ID_AA64ISAR2_EL1)

sys/arm64/include/armreg.h

1225

#define ID_AA64MMFR0_EL1_ISS ISS_MSR_REG(ID_AA64MMFR0_EL1)

sys/arm64/include/armreg.h

1332

#define ID_AA64MMFR1_EL1_ISS ISS_MSR_REG(ID_AA64MMFR1_EL1)

sys/arm64/include/armreg.h

1442

#define ID_AA64MMFR2_EL1_ISS ISS_MSR_REG(ID_AA64MMFR2_EL1)

sys/arm64/include/armreg.h

1544

#define ID_AA64MMFR3_EL1_ISS ISS_MSR_REG(ID_AA64MMFR3_EL1)

sys/arm64/include/armreg.h

1631

#define ID_AA64MMFR4_EL1_ISS ISS_MSR_REG(ID_AA64MMFR4_EL1)

sys/arm64/include/armreg.h

1640

#define ID_AA64PFR0_EL1_ISS ISS_MSR_REG(ID_AA64PFR0_EL1)

sys/arm64/include/armreg.h

1756

#define ID_AA64PFR1_EL1_ISS ISS_MSR_REG(ID_AA64PFR1_EL1)

sys/arm64/include/armreg.h

1854

#define ID_AA64PFR2_EL1_ISS ISS_MSR_REG(ID_AA64PFR2_EL1)

sys/arm64/include/armreg.h

1863

#define ID_AA64ZFR0_EL1_ISS ISS_MSR_REG(ID_AA64ZFR0_EL1)

sys/arm64/include/armreg.h

1928

#define ID_ISAR5_EL1_ISS ISS_MSR_REG(ID_ISAR5_EL1)

sys/arm64/include/armreg.h

2059

#define MVFR0_EL1_ISS ISS_MSR_REG(MVFR0_EL1)

sys/arm64/include/armreg.h

2118

#define MVFR1_EL1_ISS ISS_MSR_REG(MVFR1_EL1)

sys/arm64/include/armreg.h

250

#define CNTPCT_EL0_ISS ISS_MSR_REG(CNTPCT_EL0)

sys/arm64/include/armreg.h

350

#define CTR_EL0_ISS ISS_MSR_REG(CTR_EL0)

sys/arm64/include/armreg.h

767

#define ID_AA64AFR0_EL1_ISS ISS_MSR_REG(ID_AA64AFR0_EL1)

sys/arm64/include/armreg.h

776

#define ID_AA64AFR1_EL1_ISS ISS_MSR_REG(ID_AA64AFR1_EL1)

sys/arm64/include/armreg.h

785

#define ID_AA64DFR0_EL1_ISS ISS_MSR_REG(ID_AA64DFR0_EL1)

sys/arm64/include/armreg.h

892

#define ID_AA64DFR1_EL1_ISS ISS_MSR_REG(ID_AA64DFR1_EL1)

sys/arm64/include/armreg.h

919

#define ID_AA64ISAR0_EL1_ISS ISS_MSR_REG(ID_AA64ISAR0_EL1)

sys/arm64/vmm/io/vgic_v3.c

1920

vm_register_reg_handler(vm, ISS_MSR_REG(ICC_SGI1R_EL1),