IPU_WRITE4
IPU_WRITE4(sc, IPU_CONF, reg);
IPU_WRITE4(sc, off, reg);
IPU_WRITE4(sc, IPU_DISP_GEN, reg);
IPU_WRITE4(sc, addr, reg);
IPU_WRITE4(sc, addr, reg);
IPU_WRITE4(sc, addr, reg);
IPU_WRITE4(sc, addr, 0);
IPU_WRITE4(sc, addr, 0);
IPU_WRITE4(sc, addr, reg);
IPU_WRITE4(sc, addr, w1);
IPU_WRITE4(sc, addr + sizeof(uint32_t), w2);
IPU_WRITE4(sc, bs_clkgen_offset, DI_BS_CLKGEN0(div, 0));
IPU_WRITE4(sc, bs_clkgen_offset + 4, DI_BS_CLKGEN1_DOWN(div / 2, div % 2));
IPU_WRITE4(sc, dw_gen_offset, dw_gen);
IPU_WRITE4(sc, dw_set_offset, dw_set);
IPU_WRITE4(sc, di_scr_conf, sc->sc_mode->vtotal - 1);
IPU_WRITE4(sc, gen_offset, gen);
IPU_WRITE4(sc, as_gen_offset, as_gen);
IPU_WRITE4(sc, (di ? IPU_DI1_POL : IPU_DI0_POL), DI_POL_DRDY_POLARITY_15);
IPU_WRITE4(sc, DC_DISP_CONF2(di), sc->sc_mode->hdisplay);
IPU_WRITE4(sc, DC_WRITE_CH_CONF_1, WRITE_CH_CONF_PROG_DI_ID(1));
IPU_WRITE4(sc, DC_WRITE_CH_CONF_5, conf);
IPU_WRITE4(sc, offset, reg);
IPU_WRITE4(sc, DC_MAP_CONF_VAL(ptr), reg);
IPU_WRITE4(sc, DC_MAP_CONF_PTR(map), reg);
IPU_WRITE4(sc, DC_MAP_CONF_VAL(map), reg);
IPU_WRITE4(sc, DC_WRITE_CH_CONF_5, conf);
IPU_WRITE4(sc, DC_WRITE_CH_ADDR_5, 0x00000000);
IPU_WRITE4(sc, DC_GEN, DC_GEN_SYNC_PRIORITY | DC_GEN_SYNC); /* High priority, sync */
IPU_WRITE4(sc, DMFC_IC_CTRL, DMFC_IC_CTRL_DISABLED);
IPU_WRITE4(sc, DMFC_WR_CHAN, DMFC_WR_CHAN_BURST_SIZE_8 |
IPU_WRITE4(sc, DMFC_WR_CHAN_DEF, DMFC_WR_CHAN_DEF_WM_CLR_2C(1) |
IPU_WRITE4(sc, DMFC_DP_CHAN,
IPU_WRITE4(sc, DMFC_DP_CHAN_DEF, DMFC_DP_CHAN_DEF_WM_CLR_6F(1) |
IPU_WRITE4(sc, DMFC_GENERAL_1, reg);
IPU_WRITE4(sc, db_mode_sel, reg);
IPU_WRITE4(sc, cur_buf, (1UL << (DMA_CHANNEL & 0x1f)));
IPU_WRITE4(sc, IPU_CONF, DI_PORT ? IPU_CONF_DI1_EN : IPU_CONF_DI0_EN);
IPU_WRITE4(sc, IPU_MEM_RST, IPU_MEM_RST_ALL);