sys/arm/freescale/imx/imx_gpio.c

551

pad = READ4(sc, IMX_GPIO_DR_REG);

sys/arm/freescale/imx/imx_gpio.c

555

SET4(sc, IMX_GPIO_DR_REG, (pad << pin->gp_pin));

sys/arm/freescale/imx/imx_gpio.c

661

SET4(sc, IMX_GPIO_DR_REG, (1U << pin));

sys/arm/freescale/imx/imx_gpio.c

663

CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin));

sys/arm/freescale/imx/imx_gpio.c

692

*val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1;

sys/arm/freescale/imx/imx_gpio.c

708

WRITE4(sc, IMX_GPIO_DR_REG,

sys/arm/freescale/imx/imx_gpio.c

709

(READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin)));

sys/arm/freescale/imx/imx_gpio.c

727

*orig_pins = READ4(sc, IMX_GPIO_DR_REG);

sys/arm/freescale/imx/imx_gpio.c

731

WRITE4(sc, IMX_GPIO_DR_REG,

sys/arm/freescale/imx/imx_gpio.c

732

(READ4(sc, IMX_GPIO_DR_REG) & ~clear_pins) ^ change_pins);

sys/arm/freescale/imx/imx_gpio.c

753

pads = READ4(sc, IMX_GPIO_DR_REG);

sys/arm/freescale/imx/imx_gpio.c

772

WRITE4(sc, IMX_GPIO_DR_REG,

sys/arm/freescale/imx/imx_gpio.c

773

(READ4(sc, IMX_GPIO_DR_REG) & ~drclr) | drset);