AR_CR
OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0)
__func__, OS_REG_READ(ah, AR_CR));
OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0);
OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1); /* enable altq xmit */
OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0);
OS_REG_WRITE(ah, AR_CR, 0);
OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
, OS_REG_READ(ah, AR_CR)
OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
OS_REG_READ(ah, AR_CR),
OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD);
if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) {
OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
OS_REG_READ(ah, AR_CR),
DEFBASICfmt(AR_CR, "CR", AR_CR_BITS),
DEFBASICfmt(AR_CR, "CR", AR_CR_BITS),
DEFBASIC(AR_CR, "CR"),
DEFBASIC(AR_CR, "CR"),