AQ_READ_REG
v = AQ_READ_REG(hw, AQ2_MIF_BOOT_REG);
v = AQ_READ_REG(hw, AQ2_MCP_HOST_REQ_INT_REG);
v = AQ_READ_REG(hw, AQ2_MIF_BOOT_REG);
v = AQ_READ_REG(hw, AQ2_MCP_HOST_REQ_INT_REG);
return (AQ_HW_WAIT_FOR((AQ_READ_REG(hw,
v = AQ_READ_REG(hw, AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG);
mac_addr[0] = AQ_READ_REG(hw, AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG);
mac_addr[1] = AQ_READ_REG(hw, AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG + 4);
v = AQ_READ_REG(hw, AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG);
v = AQ_READ_REG(hw, AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG);
tid0 = AQ_READ_REG(hw, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG);
*data = AQ_READ_REG(hw, reg);
tid1 = AQ_READ_REG(hw, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG);
v = AQ_READ_REG(hw, AQ2_MIF_BOOT_REG);
boot_exit_code = AQ_READ_REG(hw, 0x388);
hw->fw_version.raw = AQ_READ_REG(hw, 0x18);
uint32_t spi = AQ_READ_REG(hw, 0x53c);
if ((hw->fw_version.raw = AQ_READ_REG(hw, 0x18)) != 0)
int ver = AQ_READ_REG(hw, 0x18);
union aq_fw1x_state_reg state = { .val = AQ_READ_REG(hw, AQ_HW_MPI_STATE_ADR) };
state.val, AQ_READ_REG(hw, AQ_HW_MPI_CONTROL_ADR));
uint32_t efuse_shadow_addr = AQ_READ_REG(hw, 0x374);
hi = AQ_READ_REG(hw, addr + 4);
lo = AQ_READ_REG(hw, addr);
hi = AQ_READ_REG(hw, addr + 4);
uint32_t efuse_shadow_addr = AQ_READ_REG(hw, 0x364);
if (!AQ_READ_REG(hw, 0x370)) {
err = AQ_HW_WAIT_FOR((hw->mbox_addr = AQ_READ_REG(hw, 0x360)) != 0, 400U, 20);
val = AQ_READ_REG(hw, AQ_HW_PCI_REG_CONTROL_6_ADR);
uint32_t fpgaver = AQ_READ_REG(hw, AQ2_HW_FPGA_VERSION_REG);
reg_old = AQ_READ_REG(hw, reg); \
((AQ_READ_REG(a, reg) & msk) >> shift))
#define AQ_HW_FLUSH(hw) { (void)AQ_READ_REG((hw), 0x10); }
return AQ_READ_REG(hw, glb_daisy_chain_status1_adr);
return AQ_READ_REG(aq_hw, rx_dma_stat_counter7_adr);
return AQ_READ_REG(aq_hw, glb_mif_id_adr);
return AQ_READ_REG(aq_hw, rpb_rx_dma_drop_pkt_cnt_adr);
return AQ_READ_REG(aq_hw, stats_rx_dma_good_octet_counterlsw__adr);
return AQ_READ_REG(aq_hw, stats_rx_dma_good_pkt_counterlsw__adr);
return AQ_READ_REG(aq_hw, stats_tx_dma_good_octet_counterlsw__adr);
return AQ_READ_REG(aq_hw, stats_tx_dma_good_pkt_counterlsw__adr);
return AQ_READ_REG(aq_hw, stats_rx_dma_good_octet_countermsw__adr);
return AQ_READ_REG(aq_hw, msm_reg_rd_data_adr);
return AQ_READ_REG(aq_hw, stats_rx_dma_good_pkt_countermsw__adr);
return AQ_READ_REG(hw,
return AQ_READ_REG(hw, glb_cpu_no_reset_scratchpad_adr(index));
return AQ_READ_REG(hw, mif_power_gating_enable_control_adr);
return AQ_READ_REG(hw, glb_general_provisioning9_adr);
return AQ_READ_REG(hw, glb_nvr_provisioning2_adr);
return AQ_READ_REG(aq_hw, stats_tx_dma_good_octet_countermsw__adr);
return AQ_READ_REG(hw, glb_nvr_interface1_adr);
return AQ_READ_REG(hw, mif_mcp_up_mailbox_addr_adr);
return AQ_READ_REG(hw, mif_mcp_up_mailbox_data_adr);
return AQ_READ_REG(aq_hw, stats_tx_dma_good_pkt_countermsw__adr);
return AQ_READ_REG(aq_hw, stats_rx_lo_coalesced_pkt_count0__addr);
return AQ_READ_REG(aq_hw, itr_isrlsw_adr);
return AQ_READ_REG(hw, glb_fw_image_id1_adr);
return AQ_READ_REG(aq_hw, gen_intr_stat_adr);
return AQ_READ_REG(aq_hw, glb_cpu_sem_adr(sem_index));
return AQ_READ_REG(aq_hw, rx_dma_desc_stat_adr(descriptor));
return AQ_READ_REG(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor));
return AQ_READ_REG(hw, glb_standard_ctl1_adr);
return AQ_READ_REG(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor));
return AQ_READ_REG(hw, glb_ctl2_adr);
return AQ_READ_REG(aq_hw, rpf_rss_key_rd_data_adr);