sys/dev/etherswitch/ar40xx/ar40xx_hw.c

120

AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

126

AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL1, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

132

AR40XX_REG_WRITE(sc, AR40XX_REG_MAX_FRAME_SIZE, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

137

AR40XX_REG_WRITE(sc, AR40XX_REG_MODULE_EN, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

140

AR40XX_REG_WRITE(sc, AR40XX_REG_EEE_CTRL, 0);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

145

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

351

AR40XX_REG_WRITE(sc, AR40XX_REG_SW_MAC_ADDR0, ret0);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

352

AR40XX_REG_WRITE(sc, AR40XX_REG_SW_MAC_ADDR1, ret1);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

126

AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

153

AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

155

AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA0, 0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

156

AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA1, 0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

157

AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA2, 0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

176

AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC, val);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

95

AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

136

AR40XX_REG_WRITE(sc, AR40XX_REG_MIB_FUNC, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

109

AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

115

AR40XX_REG_WRITE(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

125

AR40XX_REG_WRITE(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

83

AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

89

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

93

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_HOL_CTRL1(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

104

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port),

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

115

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

119

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

137

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), 0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

160

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

183

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

187

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

234

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

271

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

276

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

283

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

81

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), 0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

82

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_HEADER(port), 0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

83

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), 0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

353

AR40XX_REG_WRITE(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

402

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(phy + 1), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_vtu.c

92

AR40XX_REG_WRITE(sc, AR40XX_REG_VTU_FUNC0, val);

sys/dev/etherswitch/ar40xx/ar40xx_hw_vtu.c

97

AR40XX_REG_WRITE(sc, AR40XX_REG_VTU_FUNC1, op);

sys/dev/etherswitch/ar40xx/ar40xx_main.c

566

AR40XX_REG_WRITE(sc, addr, value);