sys/dev/etherswitch/ar40xx/ar40xx_hw.c

129

reg = AR40XX_REG_READ(sc, AR40XX_REG_MAX_FRAME_SIZE);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

135

reg = AR40XX_REG_READ(sc, AR40XX_REG_MODULE_EN);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

285

t = AR40XX_REG_READ(sc, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

316

ret0 = AR40XX_REG_READ(sc, AR40XX_REG_SW_MAC_ADDR0);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

317

ret1 = AR40XX_REG_READ(sc, AR40XX_REG_SW_MAC_ADDR1);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

174

val = AR40XX_REG_READ(sc, AR40XX_REG_ATU_FUNC);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

186

ret0 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

187

ret1 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA1);

sys/dev/etherswitch/ar40xx/ar40xx_hw_atu.c

188

ret2 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA2);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

133

reg = AR40XX_REG_READ(sc, AR40XX_REG_MIB_FUNC);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

184

val = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

186

reg = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset + 4);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

105

reg = AR40XX_REG_READ(sc, AR40XX_REG_FWD_CTRL0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

112

reg = AR40XX_REG_READ(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

122

reg = AR40XX_REG_READ(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

80

reg = AR40XX_REG_READ(sc, AR40XX_REG_FWD_CTRL0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

87

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(port));

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

91

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_HOL_CTRL1(port));

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

158

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(port));

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

208

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN0(port));

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

350

reg = AR40XX_REG_READ(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

400

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(phy + 1));

sys/dev/etherswitch/ar40xx/ar40xx_hw_vtu.c

179

reg = AR40XX_REG_READ(sc, AR40XX_REG_VTU_FUNC0);

sys/dev/etherswitch/ar40xx/ar40xx_main.c

183

AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(val)));

sys/dev/etherswitch/ar40xx/ar40xx_main.c

185

AR40XX_REG_READ(sc, AR40XX_REG_PORT_HEADER(val)));

sys/dev/etherswitch/ar40xx/ar40xx_main.c

187

AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN0(val)));

sys/dev/etherswitch/ar40xx/ar40xx_main.c

189

AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN1(val)));

sys/dev/etherswitch/ar40xx/ar40xx_main.c

191

AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(val)));

sys/dev/etherswitch/ar40xx/ar40xx_main.c

193

AR40XX_REG_READ(sc, AR40XX_REG_PORT_HOL_CTRL1(val)));

sys/dev/etherswitch/ar40xx/ar40xx_main.c

195

val, AR40XX_REG_READ(sc, AR40XX_REG_PORT_FLOWCTRL_THRESH(val)));

sys/dev/etherswitch/ar40xx/ar40xx_main.c

555

return AR40XX_REG_READ(sc, addr);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

95

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(phy + 1));