AQ_WRITE_REG
AQ_WRITE_REG(hw, FW1X_MPI_CONTROL_ADR, state.val);
AQ_WRITE_REG(hw, FW2X_MPI_CONTROL_ADDR, (uint32_t)value);
AQ_WRITE_REG(hw, FW2X_MPI_CONTROL_ADDR + 4, (uint32_t)(value >> 32));
AQ_WRITE_REG(hw, FW2X_MPI_LED_ADDR,
AQ_WRITE_REG(hw, AQ_HW_UCP_0X370_REG, ucp_0x370);
AQ_WRITE_REG(hw, 0x00007040U, 0x00010000U);//IS_CHIP_FEATURE(TPO2) ? 0x00010000U : 0x00000000U);
AQ_WRITE_REG(hw, 0x00005040U, control_reg_val);
AQ_WRITE_REG(hw, AQ_HW_PCI_REG_CONTROL_6_ADR, (val & ~0x707) | 0x404);
AQ_WRITE_REG(hw, AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);
AQ_WRITE_REG(hw, reg, reg_new); \
AQ_WRITE_REG(hw, reg, value); \
#define aq_hw_write_reg AQ_WRITE_REG
AQ_WRITE_REG(aq_hw, rpo_lro_en_adr, lro_en);
AQ_WRITE_REG(aq_hw, rpo_lro_rsc_max_adr, lro_pkt_lim);
AQ_WRITE_REG(aq_hw, tdm_lso_en_adr, large_send_offload_en);
AQ_WRITE_REG(aq_hw, msm_reg_wr_data_adr, reg_wr_data);
AQ_WRITE_REG(aq_hw, glb_cpu_scratch_scp_adr(scratch_scp),
AQ_WRITE_REG(hw, glb_cpu_no_reset_scratchpad_adr(index), value);
AQ_WRITE_REG(hw, mif_power_gating_enable_control_adr, value);
AQ_WRITE_REG(hw, glb_general_provisioning9_adr, value);
AQ_WRITE_REG(hw, glb_nvr_provisioning2_adr, value);
AQ_WRITE_REG(hw, glb_nvr_interface1_adr, value);
AQ_WRITE_REG(hw, mif_mcp_up_mailbox_addr_adr, value);
AQ_WRITE_REG(aq_hw, itr_iamrlsw_adr, irq_auto_masklsw);
AQ_WRITE_REG(aq_hw, itr_imcrlsw_adr, irq_msk_clearlsw);
AQ_WRITE_REG(aq_hw, itr_imsrlsw_adr, irq_msk_setlsw);
AQ_WRITE_REG(aq_hw, itr_iscrlsw_adr, irq_status_clearlsw);
AQ_WRITE_REG(hw, glb_fw_image_id1_adr, value);
AQ_WRITE_REG(aq_hw, glb_cpu_sem_adr(sem_index), sem_value);
AQ_WRITE_REG(aq_hw, gen_intr_map_adr(regidx), gen_intr_map);
AQ_WRITE_REG(aq_hw, intr_glb_ctl_adr, intr_glb_ctl);
AQ_WRITE_REG(aq_hw, intr_thr_adr(throttle), intr_thr);
AQ_WRITE_REG(aq_hw, rx_dma_desc_base_addrlsw_adr(descriptor),
AQ_WRITE_REG(aq_hw, rx_dma_desc_base_addrmsw_adr(descriptor),
AQ_WRITE_REG(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor),
AQ_WRITE_REG(aq_hw, rx_flr_mcst_flr_msk_adr, rx_flr_mcst_flr_msk);
AQ_WRITE_REG(aq_hw, rx_flr_mcst_flr_adr(filter), rx_flr_mcst_flr);
AQ_WRITE_REG(aq_hw, rx_flr_rss_control1_adr, rx_flr_rss_control1);
AQ_WRITE_REG(aq_hw, rx_flr_control2_adr, rx_filter_control2);
AQ_WRITE_REG(aq_hw, rx_intr_moderation_ctl_adr(queue),
AQ_WRITE_REG(aq_hw, tx_dma_debug_ctl_adr, tx_dma_debug_ctl);
AQ_WRITE_REG(aq_hw, tx_dma_desc_base_addrlsw_adr(descriptor),
AQ_WRITE_REG(aq_hw, tx_dma_desc_base_addrmsw_adr(descriptor),
AQ_WRITE_REG(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor),
AQ_WRITE_REG(aq_hw, tx_intr_moderation_ctl_adr(queue),
AQ_WRITE_REG(hw, glb_standard_ctl1_adr, glb_standard_ctl1);
AQ_WRITE_REG(hw, glb_ctl2_adr, global_ctl2);
AQ_WRITE_REG(aq_hw, rpfl2uc_daflsw_adr(filter),
AQ_WRITE_REG(aq_hw, rpf_rss_key_wr_data_adr, rss_key_wr_data);
AQ_WRITE_REG(hw, glb_daisy_chain_status1_adr, glb_daisy_chain_status1);