sys/dev/arcmsr/arcmsr.c

1086

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);

sys/dev/arcmsr/arcmsr.c

1088

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);

sys/dev/arcmsr/arcmsr.c

1192

struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;

sys/dev/arcmsr/arcmsr.c

1237

struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;

sys/dev/arcmsr/arcmsr.c

1281

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);

sys/dev/arcmsr/arcmsr.c

1321

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);

sys/dev/arcmsr/arcmsr.c

1368

CHIP_REG_WRITE32(HBA_MessageUnit,

sys/dev/arcmsr/arcmsr.c

1744

devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);

sys/dev/arcmsr/arcmsr.c

1845

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);

sys/dev/arcmsr/arcmsr.c

1846

outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);

sys/dev/arcmsr/arcmsr.c

1918

doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);

sys/dev/arcmsr/arcmsr.c

1919

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

2065

while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,

sys/dev/arcmsr/arcmsr.c

2258

outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;

sys/dev/arcmsr/arcmsr.c

2263

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

2487

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

274

intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */

sys/dev/arcmsr/arcmsr.c

275

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);

sys/dev/arcmsr/arcmsr.c

320

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);

sys/dev/arcmsr/arcmsr.c

3375

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);

sys/dev/arcmsr/arcmsr.c

3470

outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;

sys/dev/arcmsr/arcmsr.c

3471

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

3474

if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,

sys/dev/arcmsr/arcmsr.c

368

if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {

sys/dev/arcmsr/arcmsr.c

369

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

3765

size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/

sys/dev/arcmsr/arcmsr.c

3766

size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/

sys/dev/arcmsr/arcmsr.c

3767

size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);

sys/dev/arcmsr/arcmsr.c

3770

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

3795

acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/

sys/dev/arcmsr/arcmsr.c

3796

acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/

sys/dev/arcmsr/arcmsr.c

3797

acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/

sys/dev/arcmsr/arcmsr.c

3798

acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/

sys/dev/arcmsr/arcmsr.c

3799

acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */

sys/dev/arcmsr/arcmsr.c

4100

while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)

sys/dev/arcmsr/arcmsr.c

4175

outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);

sys/dev/arcmsr/arcmsr.c

4176

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

4177

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);

sys/dev/arcmsr/arcmsr.c

4236

CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4237

CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);

sys/dev/arcmsr/arcmsr.c

4238

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

469

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);

sys/dev/arcmsr/arcmsr.c

649

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);

sys/dev/arcmsr/arcmsr.c

902

outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;

sys/dev/arcmsr/arcmsr.c

903

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

904

while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {

sys/dev/arcmsr/arcmsr.h

899

struct HBA_MessageUnit hbamu;