sys/arm/mv/mvebu_gpio.c

128

SYSCON_WRITE_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg,

sys/arm/mv/mvebu_gpio.c

140

sc->offset + GPIO_REGNUM(pin->gp_pin) + reg);

sys/arm/mv/mvebu_gpio.c

152

SYSCON_MODIFY_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg,

sys/arm/mv/mvebu_gpio.c

318

sc->offset + GPIO_REGNUM(mgi->irq) + reg, 1 << bit,

sys/arm/mv/mvebu_gpio.c

342

sc->offset + GPIO_REGNUM(mgi->irq) + GPIO_INT_CAUSE,

sys/arm/nvidia/tegra_gpio.c

157

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp);

sys/arm/nvidia/tegra_gpio.c

167

val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin));

sys/arm/nvidia/tegra_gpio.c

349

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);

sys/arm/nvidia/tegra_gpio.c

361

tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq));

sys/arm/nvidia/tegra_gpio.c

364

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);

sys/arm/nvidia/tegra_gpio.c

409

GPIO_REGNUM(basepin));

sys/arm/nvidia/tegra_gpio.c

411

GPIO_REGNUM(basepin));

sys/arm/nvidia/tegra_gpio.c

788

bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0);

sys/arm/nvidia/tegra_gpio.c

789

bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF);

sys/arm/nvidia/tegra_gpio.c

790

bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF);