sys/arm64/arm64/gic_v3.c

1435

offset += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/arm64/gic_v3.c

1493

gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0,

sys/arm64/arm64/gic_v3.c

1497

gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0,

sys/arm64/arm64/gic_v3.c

1500

gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ISENABLER0,

sys/arm64/arm64/gic_v3.c

1505

gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_IPRIORITYR(i),

sys/arm64/arm64/gic_v3.c

876

GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));

sys/arm64/arm64/gic_v3.c

886

GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);

sys/arm64/arm64/gic_v3.c

978

gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),

sys/arm64/arm64/gic_v3.c

999

gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),

sys/arm64/arm64/gic_v3_acpi.c

152

count = GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE;

sys/arm64/vmm/io/vgic_v3.c

1635

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

1664

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

1679

} else if (reg < (GICR_SGI_BASE + GICR_SGI_BASE_SIZE)) {

sys/arm64/vmm/io/vgic_v3.c

1713

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

1741

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

1754

} else if (reg < (GICR_SGI_BASE + GICR_SGI_BASE_SIZE)) {

sys/arm64/vmm/io/vgic_v3.c

1887

GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE))

sys/arm64/vmm/io/vgic_v3.c

1901

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

576

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);