sys/arm64/arm64/gic_v3.c

1435

offset += (GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/arm64/gic_v3_acpi.c

152

count = GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE;

sys/arm64/vmm/io/vgic_v3.c

1635

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

1664

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

1675

if (reg < GICR_RD_BASE_SIZE) {

sys/arm64/vmm/io/vgic_v3.c

1713

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

1741

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

1750

if (reg < GICR_RD_BASE_SIZE) {

sys/arm64/vmm/io/vgic_v3.c

1887

GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE))

sys/arm64/vmm/io/vgic_v3.c

1901

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);

sys/arm64/vmm/io/vgic_v3.c

576

(GICR_RD_BASE_SIZE + GICR_SGI_BASE_SIZE);