GICD_ITARGETSR
(gic_d_read_4(sc, GICD_ITARGETSR(i)) >> 8 * (i & 0x3)) &
mask = gic_d_read_4(sc, GICD_ITARGETSR(4 * i));
gic_d_write_4(sc, GICD_ITARGETSR(i), mask);
gic_d_write_1(sc, GICD_ITARGETSR(0) + irq, mask);
VGIC_REGISTER_RANGE_RAZ_WI(GICD_ITARGETSR(0), GICD_ITARGETSR(1024), 4,