GICD_ISPENDR
!!(gic_d_read_4(sc, GICD_ISPENDR(i)) & GICD_I_MASK(i)),
n = (reg - GICD_ISPENDR(0)) / 4;
n = (reg - GICD_ISPENDR(0)) / 4;
VGIC_REGISTER_RAZ_WI(GICD_ISPENDR(0), 4, VGIC_32_BIT),
VGIC_REGISTER_RANGE(GICD_ISPENDR(32), GICD_ISPENDR(1024), 4,