sys/arm/arm/gic.c

1213

!!(gic_d_read_4(sc, GICD_ISENABLER(i)) & GICD_I_MASK(i)),

sys/arm/arm/gic.c

170

gic_d_write_4(sc, GICD_ISENABLER(irq), GICD_I_MASK(irq));

sys/arm64/arm64/gic_v3.c

1034

gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));

sys/arm64/arm64/gic_v3.c

999

gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq),

sys/arm64/vmm/io/vgic_v3.c

1081

n = (reg - GICD_ISENABLER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1095

n = (reg - GICD_ISENABLER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1121

n = (reg - GICD_ISENABLER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

267

VGIC_REGISTER_RAZ_WI(GICD_ISENABLER(0), 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

268

VGIC_REGISTER_RANGE(GICD_ISENABLER(32), GICD_ISENABLER(1024), 4,