GICD_ISACTIVER
!!(gic_d_read_4(sc, GICD_ISACTIVER(i)) & GICD_I_MASK(i)));
n = (reg - GICD_ISACTIVER(0)) / 4;
n = (reg - GICD_ISACTIVER(0)) / 4;
VGIC_REGISTER_RAZ_WI(GICD_ISACTIVER(0), 4, VGIC_32_BIT),
VGIC_REGISTER_RANGE(GICD_ISACTIVER(32), GICD_ISACTIVER(1024), 4,