sys/arm/arm/gic.c

1222

val = gic_d_read_4(sc, GICD_ICFGR(i)) >> 2 * (i & 0xf);

sys/arm/arm/gic.c

372

gic_d_write_4(sc, GICD_ICFGR(i), GIC_DEFAULT_ICFGR_INIT);

sys/arm/arm/gic.c

645

reg = gic_d_read_4(sc, GICD_ICFGR(irq));

sys/arm/arm/gic.c

667

gic_d_write_4(sc, GICD_ICFGR(irq), reg);

sys/arm64/arm64/gic_v3.c

1335

gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000);

sys/arm64/arm64/gic_v3.c

876

GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));

sys/arm64/arm64/gic_v3.c

878

reg = gic_d_read(sc, 4, GICD_ICFGR(irq));

sys/arm64/arm64/gic_v3.c

886

GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);

sys/arm64/arm64/gic_v3.c

889

gic_d_write(sc, 4, GICD_ICFGR(irq), reg);

sys/arm64/vmm/io/vgic_v3.c

1265

n = (reg - GICD_ICFGR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1279

n = (reg - GICD_ICFGR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

300

VGIC_REGISTER_RANGE_RAZ_WI(GICD_ICFGR(0), GICD_ICFGR(32), 4,

sys/arm64/vmm/io/vgic_v3.c

302

VGIC_REGISTER_RANGE(GICD_ICFGR(32), GICD_ICFGR(1024), 4,