sys/arm/arm/gic.c

177

gic_d_write_4(sc, GICD_ICENABLER(irq), GICD_I_MASK(irq));

sys/arm/arm/gic.c

377

gic_d_write_4(sc, GICD_ICENABLER(i), 0xFFFFFFFF);

sys/arm64/arm64/gic_v3.c

1349

gic_d_write(sc, 4, GICD_ICENABLER(i), 0xFFFFFFFF);

sys/arm64/arm64/gic_v3.c

978

gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq),

sys/arm64/arm64/gic_v3.c

983

gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));

sys/arm64/vmm/io/vgic_v3.c

1107

n = (reg - GICD_ICENABLER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

271

VGIC_REGISTER_RAZ_WI(GICD_ICENABLER(0), 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

272

VGIC_REGISTER_RANGE(GICD_ICENABLER(32), GICD_ICENABLER(1024), 4,