GATE_PLL
GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0),
GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22),
GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0),
GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16),
GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
GATE_PLL(0, "pllA_out0", "pllA_out1_div", PLLA_OUT, 0),
GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
GATE_PLL(0, "pllU_out1", "pllU_out1_div", PLLU_OUTA, 0),
GATE_PLL(0, "pllU_out2", "pllU_out2_div", PLLU_OUTA, 16),
GATE_PLL(0, "pllREFE_out1", "pllREFE_out1_div", PLLREFE_OUT, 0),
GATE_PLL(0, "pllC4_out3", "pllC4_out3_div", PLLC4_OUT, 0),
GATE_PLL(0, "pllA_out0", "pllA_out0_div", PLLA_OUT, 0),