sys/arm/nvidia/tegra_xhci.c

369

FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr));

sys/arm/nvidia/tegra_xhci.c

377

FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr));

sys/arm/nvidia/tegra_xhci.c

378

FPCI_WR4(sc, ARU_C11_CSBRANGE_ADDR(addr), val);

sys/arm/nvidia/tegra_xhci.c

581

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg);

sys/arm/nvidia/tegra_xhci.c

585

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);

sys/arm/nvidia/tegra_xhci.c

602

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, ARU_MAILBOX_OWNER_SW);

sys/arm/nvidia/tegra_xhci.c

610

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg);

sys/arm/nvidia/tegra_xhci.c

614

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);

sys/arm/nvidia/tegra_xhci.c

716

FPCI_WR4(sc, XUSB_CFG_ARU_SMI_INTR, reg);

sys/arm/nvidia/tegra_xhci.c

730

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER,

sys/arm/nvidia/tegra_xhci.c

735

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);

sys/arm/nvidia/tegra_xhci.c

753

FPCI_WR4(sc, XUSB_CFG_ARU_RST, ARU_RST_RESET);

sys/arm/nvidia/tegra_xhci.c

876

FPCI_WR4(sc, T_XUSB_CFG_4, reg);

sys/arm/nvidia/tegra_xhci.c

877

FPCI_WR4(sc, T_XUSB_CFG_5, (uint32_t)((uint64_t)(base_addr) >> 32));

sys/arm/nvidia/tegra_xhci.c

884

FPCI_WR4(sc, T_XUSB_CFG_1, reg);