sys/dev/cxgbe/common/t4_hw.c

8937

t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);

sys/dev/cxgbe/common/t4_hw.c

8938

t4_write_reg(adap, EPIO_REG(DATA2), mask1);

sys/dev/cxgbe/common/t4_hw.c

8939

t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);

sys/dev/cxgbe/common/t4_hw.c

8946

t4_write_reg(adap, EPIO_REG(DATA0), mask0);

sys/dev/cxgbe/common/t4_hw.c

8947

t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);

sys/dev/cxgbe/common/t4_hw.c

8948

t4_read_reg(adap, EPIO_REG(OP)); /* flush */

sys/dev/cxgbe/common/t4_hw.c

8949

if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)

sys/dev/cxgbe/common/t4_hw.c

8953

t4_write_reg(adap, EPIO_REG(DATA0), crc);

sys/dev/cxgbe/common/t4_hw.c

8954

t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);

sys/dev/cxgbe/common/t4_hw.c

8955

t4_read_reg(adap, EPIO_REG(OP)); /* flush */

sys/dev/cxgbe/common/t4_hw.c

8956

if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)