EMAC_WRITE_REG
EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data);
EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]);
EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]);
EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr);
EMAC_WRITE_REG(sc, EMAC_CTL, 0);
EMAC_WRITE_REG(sc, EMAC_CTL, 1);
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0);
EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD);
EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 |
EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8));
EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL);
EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 |
EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 |
EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo);
EMAC_WRITE_REG(sc, reg, m->m_len);
EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);
EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);