ENETC_PORT_WR4
ENETC_PORT_WR4(sc, ENETC_PSIPMR, reg);
ENETC_PORT_WR4(sc, ENETC_PSIPMAR0(0), low);
ENETC_PORT_WR4(sc, ENETC_PRSSK(i), reg);
ENETC_PORT_WR4(sc, ENETC_PM0_CMD_CFG,
ENETC_PORT_WR4(sc, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
ENETC_PORT_WR4(sc, ENETC_PSICFGR0(0), val);
ENETC_PORT_WR4(sc, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VUTA(1));
ENETC_PORT_WR4(sc, ENETC_PVCLCTR, ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
ENETC_PORT_WR4(sc, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
ENETC_PORT_WR4(sc, ENETC_PAR_PORT_CFG, ENETC_PAR_PORT_L4CD);
ENETC_PORT_WR4(sc, ENETC_PMR, ENETC_PMR_SI0EN | ENETC_PMR_PSPEED_1000M);
ENETC_PORT_WR4(sc, ENETC_PSIMMHFR0(0, revid == 1), bitmap & UINT32_MAX);
ENETC_PORT_WR4(sc, ENETC_PSIMMHFR1(0), bitmap >> 32);
ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX);
ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32);
ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX);
ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32);
ENETC_PORT_WR4(sc, ENETC_PM0_MAXFRM, max_frame_length);
ENETC_PORT_WR4(sc, ENETC_PTCMSDUR(0), max_frame_length);
ENETC_PORT_WR4(sc, ENETC_PTXMBAR, 2 * max_frame_length);
ENETC_PORT_WR4(sc, ENETC_PSIPVMR,
ENETC_PORT_WR4(sc, ENETC_PSIPVMR,