EFX_STATIC_ASSERT
EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
EFX_STATIC_ASSERT(sizeof (uint32_t) ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_HOST ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_HOST ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_MAC ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_PORT ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_MAC ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_PORT ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_ETHER_TYPE ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_INNER_VID ==
EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(ef10_filter_encap_list) <=
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_OUTER_VID ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_IP_PROTO ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_VNI_OR_VSID ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_IFRM_LOC_MAC ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST ==
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_UNKNOWN_MCAST_DST ==
EFX_STATIC_ASSERT((uint32_t)EFX_FILTER_MATCH_UNKNOWN_UCAST_DST ==
EFX_STATIC_ASSERT(sizeof (spec->efs_rem_host) ==
EFX_STATIC_ASSERT(sizeof (spec->efs_loc_host) ==
EFX_STATIC_ASSERT((sizeof (efx_filter_spec_t) % sizeof (uint32_t))
EFX_STATIC_ASSERT((EFX_FIELD_OFFSET(efx_filter_spec_t, efs_outer_vid) %
EFX_STATIC_ASSERT(sizeof (*header) == EFX_IMAGE_HEADER_SIZE);
EFX_STATIC_ASSERT(sizeof (*trailer) == EFX_IMAGE_TRAILER_SIZE);
EFX_STATIC_ASSERT(sizeof (chunk_hdr) == SIGNED_IMAGE_CHUNK_HDR_LEN);
EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK);
EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK);
EFX_STATIC_ASSERT(EFX_PHY_CAP_##_cap == MC_CMD_PHY_CAP_##_cap##_LBN)
EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_LEN <=
EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_SFT9001_LEN <=
EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MRSFP_LEN <=
EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MEM_LEN <=
EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
EFX_STATIC_ASSERT(MC_CMD_MEDIA_XAUI == EFX_PHY_MEDIA_XAUI);
EFX_STATIC_ASSERT(MC_CMD_MEDIA_CX4 == EFX_PHY_MEDIA_CX4);
EFX_STATIC_ASSERT(MC_CMD_MEDIA_KX4 == EFX_PHY_MEDIA_KX4);
EFX_STATIC_ASSERT(MC_CMD_MEDIA_XFP == EFX_PHY_MEDIA_XFP);
EFX_STATIC_ASSERT(MC_CMD_MEDIA_SFP_PLUS == EFX_PHY_MEDIA_SFP_PLUS);
EFX_STATIC_ASSERT(MC_CMD_MEDIA_BASE_T == EFX_PHY_MEDIA_BASE_T);
EFX_STATIC_ASSERT(MC_CMD_MEDIA_QSFP_PLUS == EFX_PHY_MEDIA_QSFP_PLUS);
EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN == 0);
EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN == 0);
EFX_STATIC_ASSERT(EFX_PHY_MEDIA_INFO_PAGE_SIZE <= 0xFF);
EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__efx_loopback_type_name) ==
EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
EFX_STATIC_ASSERT(sizeof (efx_dword_t) ==
EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
EFX_STATIC_ASSERT(EFX_EV_TX_NLABELS ==
EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS));
EFX_STATIC_ASSERT(TAG_NAME_END_DECODE == EFX_VPD_END);
EFX_STATIC_ASSERT(TAG_NAME_ID_STRING_DECODE == EFX_VPD_ID);
EFX_STATIC_ASSERT(TAG_NAME_VPD_R_DECODE == EFX_VPD_RO);
EFX_STATIC_ASSERT(TAG_NAME_VPD_W_DECODE == EFX_VPD_RW);
EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
EFX_STATIC_ASSERT(MC_CMD_SENSOR_STATE_ ## _field \
EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
EFX_STATIC_ASSERT(SIENA_MC_DYNAMIC_CONFIG_VERSION == 0);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
EFX_STATIC_ASSERT(SIENA_MC_STATIC_CONFIG_VERSION == 0);