sys/dev/sfxge/common/ef10_ev.c

802

EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);

sys/dev/sfxge/common/ef10_ev.c

947

EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);

sys/dev/sfxge/common/ef10_filter.c

126

#define MATCH_MASK(match) (EFX_MASK32(match) << EFX_LOW_BIT(match))

sys/dev/sfxge/common/ef10_nic.c

1892

encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);

sys/dev/sfxge/common/ef10_rx.c

394

EFX_MASK32(EFX_RX_CLASS_IPV4_TCP),

sys/dev/sfxge/common/ef10_rx.c

397

EFX_MASK32(EFX_RX_CLASS_IPV4_UDP),

sys/dev/sfxge/common/ef10_rx.c

399

(type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4),

sys/dev/sfxge/common/ef10_rx.c

402

EFX_MASK32(EFX_RX_CLASS_IPV6_TCP),

sys/dev/sfxge/common/ef10_rx.c

405

EFX_MASK32(EFX_RX_CLASS_IPV6_UDP),

sys/dev/sfxge/common/ef10_rx.c

407

(type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6));

sys/dev/sfxge/common/efx_intr.c

417

if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL))

sys/dev/sfxge/common/efx_mcdi.c

282

seq = emip->emi_seq++ & EFX_MASK32(MCDI_HEADER_SEQ);

sys/dev/sfxge/common/efx_mcdi.c

386

(seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) {

sys/dev/sfxge/common/efx_mcdi.c

777

(seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) {

sys/dev/sfxge/common/efx_types.h

1226

EFX_INSERT_FIELD32(_min, _max, _field, EFX_MASK32(_field))

sys/dev/sfxge/common/efx_types.h

457

EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))

sys/dev/sfxge/common/efx_types.h

461

EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))

sys/dev/sfxge/common/efx_types.h

465

EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))

sys/dev/sfxge/common/efx_types.h

469

EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))

sys/dev/sfxge/common/efx_types.h

473

EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))

sys/dev/sfxge/common/siena_nic.c

161

encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);