sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

149

EDMA_REG_WRITE(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

173

EDMA_REG_WRITE(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

189

EDMA_REG_WRITE(sc, EDMA_REG_TX_INT_MASK_Q(i), 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

194

EDMA_REG_WRITE(sc, EDMA_REG_RX_INT_MASK_Q(i), 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

198

EDMA_REG_WRITE(sc, EDMA_REG_MISC_IMR, 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

199

EDMA_REG_WRITE(sc, EDMA_REG_WOL_IMR, 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

213

EDMA_REG_WRITE(sc, EDMA_REG_RX_INT_MASK_Q(rxq), state ? 1 : 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

227

EDMA_REG_WRITE(sc, EDMA_REG_TX_INT_MASK_Q(txq), state ? 1 : 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

242

EDMA_REG_WRITE(sc, EDMA_REG_TX_ISR, 0xffff);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

244

EDMA_REG_WRITE(sc, EDMA_REG_TX_INT_MASK_Q(i),

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

249

EDMA_REG_WRITE(sc, EDMA_REG_RX_ISR, 0xff);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

251

EDMA_REG_WRITE(sc, EDMA_REG_RX_INT_MASK_Q(i),

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

256

EDMA_REG_WRITE(sc, EDMA_REG_MISC_IMR, 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

257

EDMA_REG_WRITE(sc, EDMA_REG_WOL_IMR, 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

271

EDMA_REG_WRITE(sc, EDMA_REG_RX_ISR, 0xff);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

272

EDMA_REG_WRITE(sc, EDMA_REG_TX_ISR, 0xffff);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

273

EDMA_REG_WRITE(sc, EDMA_REG_MISC_ISR, 0x1fff);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

274

EDMA_REG_WRITE(sc, EDMA_REG_WOL_ISR, 0x1);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

289

EDMA_REG_WRITE(sc, EDMA_REG_RX_ISR, (1U << rx_queue));

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

305

EDMA_REG_WRITE(sc, EDMA_REG_TX_ISR, (1U << tx_queue));

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

324

EDMA_REG_WRITE(sc, EDMA_REG_RSS_IDT(i), EDMA_RSS_IDT_VALUE);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

343

EDMA_REG_WRITE(sc, EDMA_REG_LB_RING, EDMA_LB_REG_VALUE);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

355

EDMA_REG_WRITE(sc, EDMA_REG_VQ_CTRL0, EDMA_VQ_REG_VALUE);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

356

EDMA_REG_WRITE(sc, EDMA_REG_VQ_CTRL1, EDMA_VQ_REG_VALUE);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

370

EDMA_REG_WRITE(sc, EDMA_REG_AXIW_CTRL_MAXWRSIZE,

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

386

EDMA_REG_WRITE(sc, EDMA_REG_RXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

392

EDMA_REG_WRITE(sc, EDMA_REG_TXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

459

EDMA_REG_WRITE(sc, EDMA_REG_RFD_IDX_Q(queue), reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

499

EDMA_REG_WRITE(sc, EDMA_REG_RX_SW_CONS_IDX_Q(queue), idx);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

519

EDMA_REG_WRITE(sc, EDMA_REG_INTR_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

523

EDMA_REG_WRITE(sc, EDMA_REG_WOL_CTRL, 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

528

EDMA_REG_WRITE(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

548

EDMA_REG_WRITE(sc, EDMA_REG_TXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

567

EDMA_REG_WRITE(sc, EDMA_REG_RSS_TYPE, sc->sc_config.rss_type);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

575

EDMA_REG_WRITE(sc, EDMA_REG_RX_DESC1, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

581

EDMA_REG_WRITE(sc, EDMA_REG_RXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

609

EDMA_REG_WRITE(sc, EDMA_REG_TPD_BASE_ADDR_Q(i),

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

622

EDMA_REG_WRITE(sc, EDMA_REG_TPD_IDX_Q(i), reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

623

EDMA_REG_WRITE(sc, EDMA_REG_TX_SW_CONS_IDX_Q(i), idx);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

626

EDMA_REG_WRITE(sc, EDMA_REG_TPD_RING_SIZE,

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

636

EDMA_REG_WRITE(sc, EDMA_REG_RFD_BASE_ADDR_Q(i),

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

650

EDMA_REG_WRITE(sc, EDMA_REG_RX_DESC0, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

653

EDMA_REG_WRITE(sc, EDMA_REG_TXF_WATER_MARK, 0);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

661

EDMA_REG_WRITE(sc, EDMA_REG_TX_SRAM_PART, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

680

EDMA_REG_WRITE(sc, EDMA_REG_TXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

698

EDMA_REG_WRITE(sc, EDMA_REG_RXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

733

EDMA_REG_WRITE(sc, EDMA_REG_TPD_IDX_Q(queue_id), reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

748

EDMA_REG_WRITE(sc, EDMA_REG_TX_SW_CONS_IDX_Q(queue_id), idx);

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

53

EDMA_REG_WRITE(sc, reg, EDMA_REG_READ(sc, (reg)) | (bits))

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

56

EDMA_REG_WRITE(sc, reg, EDMA_REG_READ(sc, (reg)) & ~(bits))