vmcs_write
vmcs_write(VMCS_ENTRY_MSR_LOAD, pmap_kextract(
vmcs_write(VMCS_ENTRY_MSR_LOAD_COUNT,
vmcs_write(VMCS_EXIT_MSR_STORE, 0);
vmcs_write(VMCS_EXIT_MSR_STORE_COUNT, 0);
vmcs_write(VMCS_HOST_TR_BASE, vmm_get_host_trbase());
vmcs_write(VMCS_HOST_GDTR_BASE, vmm_get_host_gdtrbase());
vmcs_write(VMCS_HOST_GS_BASE, vmm_get_host_gsbase());
vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls);
vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls);
vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls);
vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls);
vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls);
vmcs_write(VMCS_ENTRY_INTR_INFO, info);
vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);
vmcs_write(VMCS_ENTRY_EXCEPTION_ERROR, entryinfo >> 32);
vmcs_write(VMCS_ENTRY_INTR_INFO, info);
vmcs_write(VMCS_ENTRY_INTR_INFO, info);
vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);
vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);
vmcs_write(VMCS_GUEST_RSP, regval);
vmcs_write(VMCS_CR0_SHADOW, regval);
vmcs_write(VMCS_GUEST_CR0, crval);
vmcs_write(VMCS_GUEST_IA32_EFER, efer);
vmcs_write(VMCS_ENTRY_CTLS, entry_ctls);
vmcs_write(VMCS_CR4_SHADOW, regval);
vmcs_write(VMCS_GUEST_CR4, crval);
vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length);
vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length);
vmcs_write(VMCS_GUEST_RIP, vmexit->rip);
vmcs_write(VMCS_HOST_CR3, rcr3());
vmcs_write(VMCS_GUEST_RIP, rip);
vmcs_write(VMCS_TPR_THRESHOLD, vlapic_get_cr8(vlapic));
vmcs_write(VMCS_EOI_EXIT(vector), val);
vmcs_write(VMCS_PRI_PROC_BASED_CTLS, proc_ctls);
vmcs_write(VMCS_SEC_PROC_BASED_CTLS, proc_ctls2);
vmcs_write(VMCS_GUEST_INTR_STATUS, intr_status_new);