sys/amd64/include/vmm.h

127

struct vlapic *vlapic; /* (i) APIC device model */ \

sys/amd64/include/vmm.h

161

struct vlapic;

sys/amd64/include/vmm.h

195

DECLARE_VMMOPS_FUNC(struct vlapic *, vlapic_init, (void *vcpui));

sys/amd64/include/vmm.h

196

DECLARE_VMMOPS_FUNC(void, vlapic_cleanup, (struct vlapic *vlapic));

sys/amd64/include/vmm.h

249

struct vlapic *vm_lapic(struct vcpu *vcpu);

sys/amd64/vmm/amd/svm.c

1002

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/amd/svm.c

1006

vlapic_set_cr8(vlapic, ctrl->v_tpr);

sys/amd64/vmm/amd/svm.c

1745

struct vlapic *vlapic)

sys/amd64/vmm/amd/svm.c

1832

if (!vlapic_pending_intr(vlapic, &vector))

sys/amd64/vmm/amd/svm.c

1871

vlapic_intr_accepted(vlapic, vector);

sys/amd64/vmm/amd/svm.c

1896

v_tpr = vlapic_get_cr8(vlapic);

sys/amd64/vmm/amd/svm.c

2133

struct vlapic *vlapic;

sys/amd64/vmm/amd/svm.c

2143

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/amd/svm.c

2228

svm_inj_interrupts(svm_sc, vcpu, vlapic);

sys/amd64/vmm/amd/svm.c

2451

struct vlapic *vlapic;

sys/amd64/vmm/amd/svm.c

2475

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/amd/svm.c

2476

vlapic->ipi_exit = val;

sys/amd64/vmm/amd/svm.c

2537

struct vlapic *vlapic;

sys/amd64/vmm/amd/svm.c

2559

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/amd/svm.c

2560

*retval = vlapic->ipi_exit;

sys/amd64/vmm/amd/svm.c

2587

static struct vlapic *

sys/amd64/vmm/amd/svm.c

2591

struct vlapic *vlapic;

sys/amd64/vmm/amd/svm.c

2594

vlapic = malloc(sizeof(struct vlapic), M_SVM_VLAPIC, M_WAITOK | M_ZERO);

sys/amd64/vmm/amd/svm.c

2595

vlapic->vm = vcpu->sc->vm;

sys/amd64/vmm/amd/svm.c

2596

vlapic->vcpu = vcpu->vcpu;

sys/amd64/vmm/amd/svm.c

2597

vlapic->vcpuid = vcpu->vcpuid;

sys/amd64/vmm/amd/svm.c

2598

vlapic->apic_page = malloc_aligned(PAGE_SIZE, PAGE_SIZE, M_SVM_VLAPIC,

sys/amd64/vmm/amd/svm.c

2601

vlapic_init(vlapic);

sys/amd64/vmm/amd/svm.c

2603

return (vlapic);

sys/amd64/vmm/amd/svm.c

2607

svm_vlapic_cleanup(struct vlapic *vlapic)

sys/amd64/vmm/amd/svm.c

2610

vlapic_cleanup(vlapic);

sys/amd64/vmm/amd/svm.c

2611

free(vlapic->apic_page, M_SVM_VLAPIC);

sys/amd64/vmm/amd/svm.c

2612

free(vlapic, M_SVM_VLAPIC);

sys/amd64/vmm/amd/svm.c

999

struct vlapic *vlapic;

sys/amd64/vmm/intel/vmx.c

1464

vmx_inject_interrupts(struct vmx_vcpu *vcpu, struct vlapic *vlapic,

sys/amd64/vmm/intel/vmx.c

1546

vmx_inject_pir(vlapic);

sys/amd64/vmm/intel/vmx.c

1563

if (!vlapic_pending_intr(vlapic, &vector))

sys/amd64/vmm/intel/vmx.c

1624

vlapic_intr_accepted(vlapic, vector);

sys/amd64/vmm/intel/vmx.c

1941

struct vlapic *vlapic;

sys/amd64/vmm/intel/vmx.c

1950

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/intel/vmx.c

1953

cr8 = vlapic_get_cr8(vlapic);

sys/amd64/vmm/intel/vmx.c

1957

vlapic_set_cr8(vlapic, cr8);

sys/amd64/vmm/intel/vmx.c

2177

vmx_handle_apic_write(struct vmx_vcpu *vcpu, struct vlapic *vlapic,

sys/amd64/vmm/intel/vmx.c

2197

apic_regs = (uint32_t *)(vlapic->apic_page);

sys/amd64/vmm/intel/vmx.c

2199

vlapic_self_ipi_handler(vlapic, vector);

sys/amd64/vmm/intel/vmx.c

2207

vlapic_id_write_handler(vlapic);

sys/amd64/vmm/intel/vmx.c

2210

vlapic_ldr_write_handler(vlapic);

sys/amd64/vmm/intel/vmx.c

2213

vlapic_dfr_write_handler(vlapic);

sys/amd64/vmm/intel/vmx.c

2216

vlapic_svr_write_handler(vlapic);

sys/amd64/vmm/intel/vmx.c

2219

vlapic_esr_write_handler(vlapic);

sys/amd64/vmm/intel/vmx.c

2223

error = vlapic_icrlo_write_handler(vlapic, &retu);

sys/amd64/vmm/intel/vmx.c

2229

vlapic_lvt_write_handler(vlapic, offset);

sys/amd64/vmm/intel/vmx.c

2232

vlapic_icrtmr_write_handler(vlapic);

sys/amd64/vmm/intel/vmx.c

2235

vlapic_dcr_write_handler(vlapic);

sys/amd64/vmm/intel/vmx.c

2386

struct vlapic *vlapic;

sys/amd64/vmm/intel/vmx.c

2805

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/intel/vmx.c

2807

vmx, vcpuid, vmexit, vlapic);

sys/amd64/vmm/intel/vmx.c

2808

handled = vmx_handle_apic_write(vcpu, vlapic, qual);

sys/amd64/vmm/intel/vmx.c

2823

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/intel/vmx.c

2824

vlapic_sync_tpr(vlapic);

sys/amd64/vmm/intel/vmx.c

3046

struct vlapic *vlapic;

sys/amd64/vmm/intel/vmx.c

3055

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/intel/vmx.c

3102

vmx_inject_interrupts(vcpu, vlapic, rip);

sys/amd64/vmm/intel/vmx.c

3147

vmcs_write(VMCS_TPR_THRESHOLD, vlapic_get_cr8(vlapic));

sys/amd64/vmm/intel/vmx.c

319

static void vmx_inject_pir(struct vlapic *vlapic);

sys/amd64/vmm/intel/vmx.c

3595

struct vlapic *vlapic;

sys/amd64/vmm/intel/vmx.c

3677

vlapic = vm_lapic(vcpu->vcpu);

sys/amd64/vmm/intel/vmx.c

3678

vlapic->ipi_exit = val;

sys/amd64/vmm/intel/vmx.c

3732

struct vlapic vlapic;

sys/amd64/vmm/intel/vmx.c

3740

#define VMX_CTR_PIR(vlapic, pir_desc, notify, vector, level, msg) \

sys/amd64/vmm/intel/vmx.c

3742

VLAPIC_CTR2(vlapic, msg " assert %s-triggered vector %d", \

sys/amd64/vmm/intel/vmx.c

3744

VLAPIC_CTR1(vlapic, msg " pir0 0x%016lx", pir_desc->pir[0]); \

sys/amd64/vmm/intel/vmx.c

3745

VLAPIC_CTR1(vlapic, msg " pir1 0x%016lx", pir_desc->pir[1]); \

sys/amd64/vmm/intel/vmx.c

3746

VLAPIC_CTR1(vlapic, msg " pir2 0x%016lx", pir_desc->pir[2]); \

sys/amd64/vmm/intel/vmx.c

3747

VLAPIC_CTR1(vlapic, msg " pir3 0x%016lx", pir_desc->pir[3]); \

sys/amd64/vmm/intel/vmx.c

3748

VLAPIC_CTR1(vlapic, msg " notify: %s", notify ? "yes" : "no"); \

sys/amd64/vmm/intel/vmx.c

3756

vmx_set_intr_ready(struct vlapic *vlapic, int vector, bool level)

sys/amd64/vmm/intel/vmx.c

3763

vlapic_vtx = (struct vlapic_vtx *)vlapic;

sys/amd64/vmm/intel/vmx.c

3806

VMX_CTR_PIR(vlapic, pir_desc, notify, vector, level,

sys/amd64/vmm/intel/vmx.c

3812

vmx_pending_intr(struct vlapic *vlapic, int *vecptr)

sys/amd64/vmm/intel/vmx.c

3828

vlapic_vtx = (struct vlapic_vtx *)vlapic;

sys/amd64/vmm/intel/vmx.c

3830

lapic = vlapic->apic_page;

sys/amd64/vmm/intel/vmx.c

3839

vmexit = vm_exitinfo(vlapic->vcpu);

sys/amd64/vmm/intel/vmx.c

3861

VLAPIC_CTR1(vlapic, "HLT with non-zero PPR %d", lapic->ppr);

sys/amd64/vmm/intel/vmx.c

3891

vmx_intr_accepted(struct vlapic *vlapic, int vector)

sys/amd64/vmm/intel/vmx.c

3898

vmx_set_tmr(struct vlapic *vlapic, int vector, bool level)

sys/amd64/vmm/intel/vmx.c

3905

KASSERT(!vcpu_is_running(vlapic->vcpu, NULL),

sys/amd64/vmm/intel/vmx.c

3908

vlapic_vtx = (struct vlapic_vtx *)vlapic;

sys/amd64/vmm/intel/vmx.c

3923

vmx_enable_x2apic_mode_ts(struct vlapic *vlapic)

sys/amd64/vmm/intel/vmx.c

3930

vlapic_vtx = (struct vlapic_vtx *)vlapic;

sys/amd64/vmm/intel/vmx.c

3946

vmx_enable_x2apic_mode_vid(struct vlapic *vlapic)

sys/amd64/vmm/intel/vmx.c

3955

vlapic_vtx = (struct vlapic_vtx *)vlapic;

sys/amd64/vmm/intel/vmx.c

3972

if (vlapic->vcpuid == 0) {

sys/amd64/vmm/intel/vmx.c

3992

vmx_post_intr(struct vlapic *vlapic, int hostcpu)

sys/amd64/vmm/intel/vmx.c

4003

vmx_inject_pir(struct vlapic *vlapic)

sys/amd64/vmm/intel/vmx.c

4012

vlapic_vtx = (struct vlapic_vtx *)vlapic;

sys/amd64/vmm/intel/vmx.c

4015

VLAPIC_CTR0(vlapic, "vmx_inject_pir: "

sys/amd64/vmm/intel/vmx.c

4022

lapic = vlapic->apic_page;

sys/amd64/vmm/intel/vmx.c

4056

VLAPIC_CTR_IRR(vlapic, "vmx_inject_pir");

sys/amd64/vmm/intel/vmx.c

4085

VLAPIC_CTR2(vlapic, "vmx_inject_pir: "

sys/amd64/vmm/intel/vmx.c

4092

static struct vlapic *

sys/amd64/vmm/intel/vmx.c

4097

struct vlapic *vlapic;

sys/amd64/vmm/intel/vmx.c

4103

vlapic = malloc(sizeof(struct vlapic_vtx), M_VLAPIC, M_WAITOK | M_ZERO);

sys/amd64/vmm/intel/vmx.c

4104

vlapic->vm = vmx->vm;

sys/amd64/vmm/intel/vmx.c

4105

vlapic->vcpu = vcpu->vcpu;

sys/amd64/vmm/intel/vmx.c

4106

vlapic->vcpuid = vcpu->vcpuid;

sys/amd64/vmm/intel/vmx.c

4107

vlapic->apic_page = (struct LAPIC *)vcpu->apic_page;

sys/amd64/vmm/intel/vmx.c

4109

vlapic_vtx = (struct vlapic_vtx *)vlapic;

sys/amd64/vmm/intel/vmx.c

4114

vlapic->ops.enable_x2apic_mode = vmx_enable_x2apic_mode_ts;

sys/amd64/vmm/intel/vmx.c

4118

vlapic->ops.set_intr_ready = vmx_set_intr_ready;

sys/amd64/vmm/intel/vmx.c

4119

vlapic->ops.pending_intr = vmx_pending_intr;

sys/amd64/vmm/intel/vmx.c

4120

vlapic->ops.intr_accepted = vmx_intr_accepted;

sys/amd64/vmm/intel/vmx.c

4121

vlapic->ops.set_tmr = vmx_set_tmr;

sys/amd64/vmm/intel/vmx.c

4122

vlapic->ops.enable_x2apic_mode = vmx_enable_x2apic_mode_vid;

sys/amd64/vmm/intel/vmx.c

4126

vlapic->ops.post_intr = vmx_post_intr;

sys/amd64/vmm/intel/vmx.c

4128

vlapic_init(vlapic);

sys/amd64/vmm/intel/vmx.c

4130

return (vlapic);

sys/amd64/vmm/intel/vmx.c

4134

vmx_vlapic_cleanup(struct vlapic *vlapic)

sys/amd64/vmm/intel/vmx.c

4137

vlapic_cleanup(vlapic);

sys/amd64/vmm/intel/vmx.c

4138

free(vlapic, M_VLAPIC);

sys/amd64/vmm/io/vioapic.c

250

struct vlapic *vlapic;

sys/amd64/vmm/io/vioapic.c

255

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/io/vioapic.c

262

vlapic_reset_tmr(vlapic);

sys/amd64/vmm/io/vioapic.c

281

vlapic_set_tmr_level(vlapic, dest, phys, delmode, vector);

sys/amd64/vmm/io/vlapic.c

102

apicid = vlapic_get_id(vlapic);

sys/amd64/vmm/io/vlapic.c

1033

vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu)

sys/amd64/vmm/io/vlapic.c

1044

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1048

if (x2apic(vlapic))

sys/amd64/vmm/io/vlapic.c

1057

VLAPIC_CTR2(vlapic, "icrlo 0x%016lx triggered ipi %d", icrval, vec);

sys/amd64/vmm/io/vlapic.c

1061

vlapic_calcdest(vlapic->vm, &dmask, dest, phys, false, x2apic(vlapic));

sys/amd64/vmm/io/vlapic.c

1064

CPU_SETOF(vlapic->vcpuid, &dmask);

sys/amd64/vmm/io/vlapic.c

1067

dmask = vm_active_cpus(vlapic->vm);

sys/amd64/vmm/io/vlapic.c

1070

dmask = vm_active_cpus(vlapic->vm);

sys/amd64/vmm/io/vlapic.c

1071

CPU_CLR(vlapic->vcpuid, &dmask);

sys/amd64/vmm/io/vlapic.c

1081

VLAPIC_CTR1(vlapic, "Ignoring invalid ICR %016lx", icrval);

sys/amd64/vmm/io/vlapic.c

109

vlapic_dfr_write_handler(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1094

vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR,

sys/amd64/vmm/io/vlapic.c

1096

VLAPIC_CTR1(vlapic, "Ignoring invalid IPI %d", vec);

sys/amd64/vmm/io/vlapic.c

1101

vcpu = vm_vcpu(vlapic->vm, i);

sys/amd64/vmm/io/vlapic.c

1103

vmm_stat_incr(vlapic->vcpu, VLAPIC_IPI_SEND, 1);

sys/amd64/vmm/io/vlapic.c

1105

VLAPIC_CTR2(vlapic,

sys/amd64/vmm/io/vlapic.c

1112

vcpu = vm_vcpu(vlapic->vm, i);

sys/amd64/vmm/io/vlapic.c

1114

VLAPIC_CTR1(vlapic,

sys/amd64/vmm/io/vlapic.c

1121

if (!vlapic->ipi_exit) {

sys/amd64/vmm/io/vlapic.c

1125

i = vm_apicid2vcpuid(vlapic->vm, dest);

sys/amd64/vmm/io/vlapic.c

1126

if (i >= vm_get_maxcpus(vlapic->vm) ||

sys/amd64/vmm/io/vlapic.c

1127

i == vlapic->vcpuid)

sys/amd64/vmm/io/vlapic.c

113

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

114

if (x2apic(vlapic)) {

sys/amd64/vmm/io/vlapic.c

1142

vmexit = vm_exitinfo(vlapic->vcpu);

sys/amd64/vmm/io/vlapic.c

1146

*vm_exitinfo_cpuset(vlapic->vcpu) = ipimask;

sys/amd64/vmm/io/vlapic.c

115

VM_CTR1(vlapic->vm, "ignoring write to DFR in x2apic mode: %#x",

sys/amd64/vmm/io/vlapic.c

1157

struct vlapic *vlapic = vm_lapic(vcpu);

sys/amd64/vmm/io/vlapic.c

1159

vlapic_reset(vlapic);

sys/amd64/vmm/io/vlapic.c

1165

struct vlapic *vlapic = vm_lapic(vcpu);

sys/amd64/vmm/io/vlapic.c

1182

if (!vlapic->ipi_exit)

sys/amd64/vmm/io/vlapic.c

1202

if (!vlapic->ipi_exit) {

sys/amd64/vmm/io/vlapic.c

1217

vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val)

sys/amd64/vmm/io/vlapic.c

1221

KASSERT(x2apic(vlapic), ("SELF_IPI does not exist in xAPIC mode"));

sys/amd64/vmm/io/vlapic.c

1224

lapic_intr_edge(vlapic->vcpu, vec);

sys/amd64/vmm/io/vlapic.c

1225

vmm_stat_incr(vlapic->vcpu, VLAPIC_IPI_SEND, 1);

sys/amd64/vmm/io/vlapic.c

1226

vmm_stat_incr(vlapic->vcpu, VLAPIC_IPI_RECV, 1);

sys/amd64/vmm/io/vlapic.c

1227

VLAPIC_CTR1(vlapic, "vlapic self-ipi %d", vec);

sys/amd64/vmm/io/vlapic.c

1231

vlapic_pending_intr(struct vlapic *vlapic, int *vecptr)

sys/amd64/vmm/io/vlapic.c

1233

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1237

vlapic_update_ppr(vlapic);

sys/amd64/vmm/io/vlapic.c

1239

if (vlapic->ops.pending_intr)

sys/amd64/vmm/io/vlapic.c

1240

return ((*vlapic->ops.pending_intr)(vlapic, vecptr));

sys/amd64/vmm/io/vlapic.c

125

VLAPIC_CTR0(vlapic, "vlapic DFR in Flat Model");

sys/amd64/vmm/io/vlapic.c

1251

VLAPIC_CTR1(vlapic, "pending intr %d", vector);

sys/amd64/vmm/io/vlapic.c

1263

vlapic_intr_accepted(struct vlapic *vlapic, int vector)

sys/amd64/vmm/io/vlapic.c

1265

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1269

if (vlapic->ops.intr_accepted)

sys/amd64/vmm/io/vlapic.c

127

VLAPIC_CTR0(vlapic, "vlapic DFR in Cluster Model");

sys/amd64/vmm/io/vlapic.c

1270

return ((*vlapic->ops.intr_accepted)(vlapic, vector));

sys/amd64/vmm/io/vlapic.c

1280

VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted");

sys/amd64/vmm/io/vlapic.c

1284

VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted");

sys/amd64/vmm/io/vlapic.c

1289

vlapic->isrvec_stk_top++;

sys/amd64/vmm/io/vlapic.c

129

VLAPIC_CTR1(vlapic, "DFR in Unknown Model %#x", lapic->dfr);

sys/amd64/vmm/io/vlapic.c

1291

stk_top = vlapic->isrvec_stk_top;

sys/amd64/vmm/io/vlapic.c

1295

vlapic->isrvec_stk[stk_top] = vector;

sys/amd64/vmm/io/vlapic.c

1299

vlapic_svr_write_handler(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1304

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1307

old = vlapic->svr_last;

sys/amd64/vmm/io/vlapic.c

1308

vlapic->svr_last = new;

sys/amd64/vmm/io/vlapic.c

1317

VLAPIC_CTR0(vlapic, "vlapic is software-disabled");

sys/amd64/vmm/io/vlapic.c

1318

VLAPIC_TIMER_LOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

1319

callout_stop(&vlapic->callout);

sys/amd64/vmm/io/vlapic.c

1320

VLAPIC_TIMER_UNLOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

1321

vlapic_mask_lvts(vlapic);

sys/amd64/vmm/io/vlapic.c

1327

VLAPIC_CTR0(vlapic, "vlapic is software-enabled");

sys/amd64/vmm/io/vlapic.c

1328

if (vlapic_periodic_timer(vlapic))

sys/amd64/vmm/io/vlapic.c

1329

vlapic_icrtmr_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

133

vlapic_ldr_write_handler(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1335

vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,

sys/amd64/vmm/io/vlapic.c

1338

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1343

if (x2apic(vlapic) && mmio_access) {

sys/amd64/vmm/io/vlapic.c

1344

VLAPIC_CTR1(vlapic, "MMIO read from offset %#lx in x2APIC mode",

sys/amd64/vmm/io/vlapic.c

1350

if (!x2apic(vlapic) && !mmio_access) {

sys/amd64/vmm/io/vlapic.c

1354

VLAPIC_CTR1(vlapic, "x2APIC MSR read from offset %#lx in "

sys/amd64/vmm/io/vlapic.c

137

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1375

*data = vlapic_get_tpr(vlapic);

sys/amd64/vmm/io/vlapic.c

140

if (x2apic(vlapic)) {

sys/amd64/vmm/io/vlapic.c

141

VLAPIC_CTR1(vlapic, "ignoring write to LDR in x2apic mode: %#x",

sys/amd64/vmm/io/vlapic.c

1415

if (x2apic(vlapic))

sys/amd64/vmm/io/vlapic.c

1423

*data = vlapic_get_lvt(vlapic, offset);

sys/amd64/vmm/io/vlapic.c

1425

reg = vlapic_get_lvtptr(vlapic, offset);

sys/amd64/vmm/io/vlapic.c

143

lapic->ldr = x2apic_ldr(vlapic);

sys/amd64/vmm/io/vlapic.c

1434

*data = vlapic_get_ccr(vlapic);

sys/amd64/vmm/io/vlapic.c

1451

VLAPIC_CTR2(vlapic, "vlapic read offset %#x, data %#lx", offset, *data);

sys/amd64/vmm/io/vlapic.c

1456

vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,

sys/amd64/vmm/io/vlapic.c

1459

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

146

VLAPIC_CTR1(vlapic, "vlapic LDR set to %#x", lapic->ldr);

sys/amd64/vmm/io/vlapic.c

1466

VLAPIC_CTR2(vlapic, "vlapic write offset %#lx, data %#lx",

sys/amd64/vmm/io/vlapic.c

1473

if (x2apic(vlapic) && mmio_access) {

sys/amd64/vmm/io/vlapic.c

1474

VLAPIC_CTR2(vlapic, "MMIO write of %#lx to offset %#lx "

sys/amd64/vmm/io/vlapic.c

1482

if (!x2apic(vlapic) && !mmio_access) {

sys/amd64/vmm/io/vlapic.c

1483

VLAPIC_CTR2(vlapic, "x2APIC MSR write of %#lx to offset %#lx "

sys/amd64/vmm/io/vlapic.c

1493

vlapic_id_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

1496

vlapic_set_tpr(vlapic, data & 0xff);

sys/amd64/vmm/io/vlapic.c

1499

vlapic_process_eoi(vlapic);

sys/amd64/vmm/io/vlapic.c

1503

vlapic_ldr_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

1507

vlapic_dfr_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

151

vlapic_id_write_handler(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1511

vlapic_svr_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

1515

if (x2apic(vlapic))

sys/amd64/vmm/io/vlapic.c

1517

retval = vlapic_icrlo_write_handler(vlapic, retu);

sys/amd64/vmm/io/vlapic.c

1524

regptr = vlapic_get_lvtptr(vlapic, offset);

sys/amd64/vmm/io/vlapic.c

1526

vlapic_lvt_write_handler(vlapic, offset);

sys/amd64/vmm/io/vlapic.c

1530

vlapic_icrtmr_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

1535

vlapic_dcr_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

1539

vlapic_esr_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

1543

if (x2apic(vlapic))

sys/amd64/vmm/io/vlapic.c

1544

vlapic_self_ipi_handler(vlapic, data);

sys/amd64/vmm/io/vlapic.c

1564

vlapic_reset(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1568

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1571

lapic->id = vlapic_get_id(vlapic);

sys/amd64/vmm/io/vlapic.c

1576

vlapic_mask_lvts(vlapic);

sys/amd64/vmm/io/vlapic.c

1577

vlapic_reset_tmr(vlapic);

sys/amd64/vmm/io/vlapic.c

1580

vlapic_dcr_write_handler(vlapic);

sys/amd64/vmm/io/vlapic.c

1582

vlapic->svr_last = lapic->svr;

sys/amd64/vmm/io/vlapic.c

1586

vlapic_init(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1588

KASSERT(vlapic->vm != NULL, ("vlapic_init: vm is not initialized"));

sys/amd64/vmm/io/vlapic.c

1589

KASSERT(vlapic->vcpuid >= 0 &&

sys/amd64/vmm/io/vlapic.c

159

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1590

vlapic->vcpuid < vm_get_maxcpus(vlapic->vm),

sys/amd64/vmm/io/vlapic.c

1592

KASSERT(vlapic->apic_page != NULL, ("vlapic_init: apic_page is not "

sys/amd64/vmm/io/vlapic.c

160

lapic->id = vlapic_get_id(vlapic);

sys/amd64/vmm/io/vlapic.c

1602

mtx_init(&vlapic->timer_mtx, "vlapic timer mtx", NULL, MTX_SPIN);

sys/amd64/vmm/io/vlapic.c

1603

callout_init(&vlapic->callout, 1);

sys/amd64/vmm/io/vlapic.c

1605

vlapic->msr_apicbase = DEFAULT_APIC_BASE | APICBASE_ENABLED;

sys/amd64/vmm/io/vlapic.c

1607

if (vlapic->vcpuid == 0)

sys/amd64/vmm/io/vlapic.c

1608

vlapic->msr_apicbase |= APICBASE_BSP;

sys/amd64/vmm/io/vlapic.c

1610

vlapic->ipi_exit = false;

sys/amd64/vmm/io/vlapic.c

1612

vlapic_reset(vlapic);

sys/amd64/vmm/io/vlapic.c

1616

vlapic_cleanup(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1619

callout_drain(&vlapic->callout);

sys/amd64/vmm/io/vlapic.c

1620

mtx_destroy(&vlapic->timer_mtx);

sys/amd64/vmm/io/vlapic.c

1624

vlapic_get_apicbase(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1627

return (vlapic->msr_apicbase);

sys/amd64/vmm/io/vlapic.c

1631

vlapic_set_apicbase(struct vlapic *vlapic, uint64_t new)

sys/amd64/vmm/io/vlapic.c

1634

if (vlapic->msr_apicbase != new) {

sys/amd64/vmm/io/vlapic.c

1635

VLAPIC_CTR2(vlapic, "Changing APIC_BASE MSR from %#lx to %#lx "

sys/amd64/vmm/io/vlapic.c

1636

"not supported", vlapic->msr_apicbase, new);

sys/amd64/vmm/io/vlapic.c

1646

struct vlapic *vlapic;

sys/amd64/vmm/io/vlapic.c

1649

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/io/vlapic.c

1652

vlapic->msr_apicbase &= ~APICBASE_X2APIC;

sys/amd64/vmm/io/vlapic.c

1654

vlapic->msr_apicbase |= APICBASE_X2APIC;

sys/amd64/vmm/io/vlapic.c

1662

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1663

lapic->id = vlapic_get_id(vlapic);

sys/amd64/vmm/io/vlapic.c

1664

if (x2apic(vlapic)) {

sys/amd64/vmm/io/vlapic.c

1665

lapic->ldr = x2apic_ldr(vlapic);

sys/amd64/vmm/io/vlapic.c

1673

if (vlapic->ops.enable_x2apic_mode)

sys/amd64/vmm/io/vlapic.c

1674

(*vlapic->ops.enable_x2apic_mode)(vlapic);

sys/amd64/vmm/io/vlapic.c

1713

vlapic_post_intr(struct vlapic *vlapic, int hostcpu, int ipinum)

sys/amd64/vmm/io/vlapic.c

1724

if (vlapic->ops.post_intr)

sys/amd64/vmm/io/vlapic.c

1725

(*vlapic->ops.post_intr)(vlapic, hostcpu);

sys/amd64/vmm/io/vlapic.c

1731

vlapic_enabled(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1733

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1735

if ((vlapic->msr_apicbase & APICBASE_ENABLED) != 0 &&

sys/amd64/vmm/io/vlapic.c

1743

vlapic_set_tmr(struct vlapic *vlapic, int vector, bool level)

sys/amd64/vmm/io/vlapic.c

1749

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1758

if (vlapic->ops.set_tmr != NULL)

sys/amd64/vmm/io/vlapic.c

1759

(*vlapic->ops.set_tmr)(vlapic, vector, level);

sys/amd64/vmm/io/vlapic.c

1763

vlapic_reset_tmr(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

1767

VLAPIC_CTR0(vlapic, "vlapic resetting all vectors to edge-triggered");

sys/amd64/vmm/io/vlapic.c

1770

vlapic_set_tmr(vlapic, vector, false);

sys/amd64/vmm/io/vlapic.c

1774

vlapic_set_tmr_level(struct vlapic *vlapic, uint32_t dest, bool phys,

sys/amd64/vmm/io/vlapic.c

1786

VLAPIC_CTR1(vlapic, "Ignoring level trigger-mode for "

sys/amd64/vmm/io/vlapic.c

1792

vlapic_calcdest(vlapic->vm, &dmask, dest, phys, lowprio, false);

sys/amd64/vmm/io/vlapic.c

1794

if (!CPU_ISSET(vlapic->vcpuid, &dmask))

sys/amd64/vmm/io/vlapic.c

1797

VLAPIC_CTR1(vlapic, "vector %d set to level-triggered", vector);

sys/amd64/vmm/io/vlapic.c

1798

vlapic_set_tmr(vlapic, vector, true);

sys/amd64/vmm/io/vlapic.c

1803

vlapic_reset_callout(struct vlapic *vlapic, uint32_t ccr)

sys/amd64/vmm/io/vlapic.c

1811

VLAPIC_TIMER_LOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

1813

bt = vlapic->timer_freq_bt;

sys/amd64/vmm/io/vlapic.c

1817

binuptime(&vlapic->timer_fire_bt);

sys/amd64/vmm/io/vlapic.c

1818

bintime_add(&vlapic->timer_fire_bt, &bt);

sys/amd64/vmm/io/vlapic.c

1821

vlapic_callout_reset(vlapic, sbt);

sys/amd64/vmm/io/vlapic.c

1824

if (vlapic_periodic_timer(vlapic)) {

sys/amd64/vmm/io/vlapic.c

1825

binuptime(&vlapic->timer_fire_bt);

sys/amd64/vmm/io/vlapic.c

1826

bintime_add(&vlapic->timer_fire_bt,

sys/amd64/vmm/io/vlapic.c

1827

&vlapic->timer_period_bt);

sys/amd64/vmm/io/vlapic.c

1828

sbt = bttosbt(vlapic->timer_period_bt);

sys/amd64/vmm/io/vlapic.c

1830

callout_stop(&vlapic->callout);

sys/amd64/vmm/io/vlapic.c

1831

vlapic_callout_reset(vlapic, sbt);

sys/amd64/vmm/io/vlapic.c

1835

VLAPIC_TIMER_UNLOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

1843

struct vlapic *vlapic;

sys/amd64/vmm/io/vlapic.c

1857

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/io/vlapic.c

1860

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

1863

SNAPSHOT_VAR_OR_LEAVE(vlapic->esr_pending, meta, ret, done);

sys/amd64/vmm/io/vlapic.c

1865

SNAPSHOT_VAR_OR_LEAVE(vlapic->timer_freq_bt.sec,

sys/amd64/vmm/io/vlapic.c

1867

SNAPSHOT_VAR_OR_LEAVE(vlapic->timer_freq_bt.frac,

sys/amd64/vmm/io/vlapic.c

1875

vlapic->timer_period_bt = vlapic->timer_freq_bt;

sys/amd64/vmm/io/vlapic.c

1876

bintime_mul(&vlapic->timer_period_bt, lapic->icr_timer);

sys/amd64/vmm/io/vlapic.c

1879

SNAPSHOT_BUF_OR_LEAVE(vlapic->isrvec_stk,

sys/amd64/vmm/io/vlapic.c

1880

sizeof(vlapic->isrvec_stk),

sys/amd64/vmm/io/vlapic.c

1882

SNAPSHOT_VAR_OR_LEAVE(vlapic->isrvec_stk_top, meta, ret, done);

sys/amd64/vmm/io/vlapic.c

1884

SNAPSHOT_BUF_OR_LEAVE(vlapic->lvt_last,

sys/amd64/vmm/io/vlapic.c

1885

sizeof(vlapic->lvt_last),

sys/amd64/vmm/io/vlapic.c

1889

ccr = vlapic_get_ccr(vlapic);

sys/amd64/vmm/io/vlapic.c

1894

vlapic_enabled(vlapic) && lapic->icr_timer != 0) {

sys/amd64/vmm/io/vlapic.c

1901

vlapic_reset_callout(vlapic, ccr);

sys/amd64/vmm/io/vlapic.c

199

vlapic_get_ccr(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

206

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

208

VLAPIC_TIMER_LOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

209

if (callout_active(&vlapic->callout)) {

sys/amd64/vmm/io/vlapic.c

215

if (bintime_cmp(&vlapic->timer_fire_bt, &bt_now, >)) {

sys/amd64/vmm/io/vlapic.c

216

bt_rem = vlapic->timer_fire_bt;

sys/amd64/vmm/io/vlapic.c

218

ccr += bt_rem.sec * BT2FREQ(&vlapic->timer_freq_bt);

sys/amd64/vmm/io/vlapic.c

219

ccr += bt_rem.frac / vlapic->timer_freq_bt.frac;

sys/amd64/vmm/io/vlapic.c

224

VLAPIC_CTR2(vlapic, "vlapic ccr_timer = %#x, icr_timer = %#x",

sys/amd64/vmm/io/vlapic.c

226

VLAPIC_TIMER_UNLOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

231

vlapic_dcr_write_handler(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

236

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

237

VLAPIC_TIMER_LOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

240

VLAPIC_CTR2(vlapic, "vlapic dcr_timer=%#x, divisor=%d",

sys/amd64/vmm/io/vlapic.c

249

FREQ2BT(VLAPIC_BUS_FREQ / divisor, &vlapic->timer_freq_bt);

sys/amd64/vmm/io/vlapic.c

250

vlapic->timer_period_bt = vlapic->timer_freq_bt;

sys/amd64/vmm/io/vlapic.c

251

bintime_mul(&vlapic->timer_period_bt, lapic->icr_timer);

sys/amd64/vmm/io/vlapic.c

253

VLAPIC_TIMER_UNLOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

257

vlapic_esr_write_handler(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

261

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

262

lapic->esr = vlapic->esr_pending;

sys/amd64/vmm/io/vlapic.c

263

vlapic->esr_pending = 0;

sys/amd64/vmm/io/vlapic.c

267

vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level)

sys/amd64/vmm/io/vlapic.c

275

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

277

VLAPIC_CTR1(vlapic, "vlapic is software disabled, ignoring "

sys/amd64/vmm/io/vlapic.c

283

vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR,

sys/amd64/vmm/io/vlapic.c

285

VLAPIC_CTR1(vlapic, "vlapic ignoring interrupt to vector %d",

sys/amd64/vmm/io/vlapic.c

290

if (vlapic->ops.set_intr_ready)

sys/amd64/vmm/io/vlapic.c

291

return ((*vlapic->ops.set_intr_ready)(vlapic, vector, level));

sys/amd64/vmm/io/vlapic.c

305

VLAPIC_CTR3(vlapic, "vlapic TMR[%d] is 0x%08x but "

sys/amd64/vmm/io/vlapic.c

310

VLAPIC_CTR_IRR(vlapic, "vlapic_set_intr_ready");

sys/amd64/vmm/io/vlapic.c

315

vlapic_get_lvtptr(struct vlapic *vlapic, uint32_t offset)

sys/amd64/vmm/io/vlapic.c

317

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

369

vlapic_get_lvt(struct vlapic *vlapic, uint32_t offset)

sys/amd64/vmm/io/vlapic.c

375

val = atomic_load_acq_32(&vlapic->lvt_last[idx]);

sys/amd64/vmm/io/vlapic.c

380

vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)

sys/amd64/vmm/io/vlapic.c

386

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

387

lvtptr = vlapic_get_lvtptr(vlapic, offset);

sys/amd64/vmm/io/vlapic.c

410

atomic_store_rel_32(&vlapic->lvt_last[idx], val);

sys/amd64/vmm/io/vlapic.c

414

vlapic_mask_lvts(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

416

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

419

vlapic_lvt_write_handler(vlapic, APIC_OFFSET_CMCI_LVT);

sys/amd64/vmm/io/vlapic.c

422

vlapic_lvt_write_handler(vlapic, APIC_OFFSET_TIMER_LVT);

sys/amd64/vmm/io/vlapic.c

425

vlapic_lvt_write_handler(vlapic, APIC_OFFSET_THERM_LVT);

sys/amd64/vmm/io/vlapic.c

428

vlapic_lvt_write_handler(vlapic, APIC_OFFSET_PERF_LVT);

sys/amd64/vmm/io/vlapic.c

431

vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT0_LVT);

sys/amd64/vmm/io/vlapic.c

434

vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT1_LVT);

sys/amd64/vmm/io/vlapic.c

437

vlapic_lvt_write_handler(vlapic, APIC_OFFSET_ERROR_LVT);

sys/amd64/vmm/io/vlapic.c

441

vlapic_fire_lvt(struct vlapic *vlapic, u_int lvt)

sys/amd64/vmm/io/vlapic.c

445

reg = atomic_load_acq_32(&vlapic->lvt_last[lvt]);

sys/amd64/vmm/io/vlapic.c

455

vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR,

sys/amd64/vmm/io/vlapic.c

459

if (vlapic_set_intr_ready(vlapic, vec, false))

sys/amd64/vmm/io/vlapic.c

460

vcpu_notify_lapic(vlapic->vcpu);

sys/amd64/vmm/io/vlapic.c

463

vm_inject_nmi(vlapic->vcpu);

sys/amd64/vmm/io/vlapic.c

466

vm_inject_extint(vlapic->vcpu);

sys/amd64/vmm/io/vlapic.c

477

dump_isrvec_stk(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

482

isrptr = &vlapic->apic_page->isr0;

sys/amd64/vmm/io/vlapic.c

486

for (i = 0; i <= vlapic->isrvec_stk_top; i++)

sys/amd64/vmm/io/vlapic.c

487

printf("isrvec_stk[%d] = %d\n", i, vlapic->isrvec_stk[i]);

sys/amd64/vmm/io/vlapic.c

496

vlapic_update_ppr(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

506

isrvec = vlapic->isrvec_stk[vlapic->isrvec_stk_top];

sys/amd64/vmm/io/vlapic.c

507

tpr = vlapic->apic_page->tpr;

sys/amd64/vmm/io/vlapic.c

514

if (vlapic->isrvec_stk_top == 0 && isrvec != 0)

sys/amd64/vmm/io/vlapic.c

522

for (i = 1; i <= vlapic->isrvec_stk_top; i++) {

sys/amd64/vmm/io/vlapic.c

523

curprio = PRIO(vlapic->isrvec_stk[i]);

sys/amd64/vmm/io/vlapic.c

525

dump_isrvec_stk(vlapic);

sys/amd64/vmm/io/vlapic.c

536

isrptr = &vlapic->apic_page->isr0;

sys/amd64/vmm/io/vlapic.c

540

if (i > vlapic->isrvec_stk_top ||

sys/amd64/vmm/io/vlapic.c

541

vlapic->isrvec_stk[i] != vector) {

sys/amd64/vmm/io/vlapic.c

542

dump_isrvec_stk(vlapic);

sys/amd64/vmm/io/vlapic.c

556

vlapic->apic_page->ppr = ppr;

sys/amd64/vmm/io/vlapic.c

557

VLAPIC_CTR1(vlapic, "vlapic_update_ppr 0x%02x", ppr);

sys/amd64/vmm/io/vlapic.c

561

vlapic_sync_tpr(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

563

vlapic_update_ppr(vlapic);

sys/amd64/vmm/io/vlapic.c

569

vlapic_process_eoi(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

571

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

582

if (vlapic->isrvec_stk_top <= 0) {

sys/amd64/vmm/io/vlapic.c

584

vlapic->isrvec_stk_top);

sys/amd64/vmm/io/vlapic.c

588

VLAPIC_CTR1(vlapic, "EOI vector %d", vector);

sys/amd64/vmm/io/vlapic.c

589

VLAPIC_CTR_ISR(vlapic, "vlapic_process_eoi");

sys/amd64/vmm/io/vlapic.c

590

vlapic->isrvec_stk_top--;

sys/amd64/vmm/io/vlapic.c

591

vlapic_update_ppr(vlapic);

sys/amd64/vmm/io/vlapic.c

593

vioapic_process_eoi(vlapic->vm, vector);

sys/amd64/vmm/io/vlapic.c

598

VLAPIC_CTR0(vlapic, "Gratuitous EOI");

sys/amd64/vmm/io/vlapic.c

599

vmm_stat_incr(vlapic->vcpu, VLAPIC_GRATUITOUS_EOI, 1);

sys/amd64/vmm/io/vlapic.c

610

vlapic_periodic_timer(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

614

lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);

sys/amd64/vmm/io/vlapic.c

622

vlapic_set_error(struct vlapic *vlapic, uint32_t mask, bool lvt_error)

sys/amd64/vmm/io/vlapic.c

625

vlapic->esr_pending |= mask;

sys/amd64/vmm/io/vlapic.c

63

#define x2apic(vlapic) (((vlapic)->msr_apicbase & APICBASE_X2APIC) ? 1 : 0)

sys/amd64/vmm/io/vlapic.c

634

if (vlapic_fire_lvt(vlapic, APIC_LVT_ERROR)) {

sys/amd64/vmm/io/vlapic.c

635

vmm_stat_incr(vlapic->vcpu, VLAPIC_INTR_ERROR, 1);

sys/amd64/vmm/io/vlapic.c

642

vlapic_fire_timer(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

645

KASSERT(VLAPIC_TIMER_LOCKED(vlapic), ("vlapic_fire_timer not locked"));

sys/amd64/vmm/io/vlapic.c

647

if (vlapic_fire_lvt(vlapic, APIC_LVT_TIMER)) {

sys/amd64/vmm/io/vlapic.c

648

VLAPIC_CTR0(vlapic, "vlapic timer fired");

sys/amd64/vmm/io/vlapic.c

649

vmm_stat_incr(vlapic->vcpu, VLAPIC_INTR_TIMER, 1);

sys/amd64/vmm/io/vlapic.c

657

vlapic_fire_cmci(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

660

if (vlapic_fire_lvt(vlapic, APIC_LVT_CMCI)) {

sys/amd64/vmm/io/vlapic.c

661

vmm_stat_incr(vlapic->vcpu, VLAPIC_INTR_CMC, 1);

sys/amd64/vmm/io/vlapic.c

669

vlapic_trigger_lvt(struct vlapic *vlapic, int vector)

sys/amd64/vmm/io/vlapic.c

672

if (vlapic_enabled(vlapic) == false) {

sys/amd64/vmm/io/vlapic.c

680

vm_inject_extint(vlapic->vcpu);

sys/amd64/vmm/io/vlapic.c

683

vm_inject_nmi(vlapic->vcpu);

sys/amd64/vmm/io/vlapic.c

699

if (vlapic_fire_lvt(vlapic, vector)) {

sys/amd64/vmm/io/vlapic.c

700

vmm_stat_array_incr(vlapic->vcpu, LVTS_TRIGGERRED,

sys/amd64/vmm/io/vlapic.c

71

#define VLAPIC_TIMER_LOCK(vlapic) mtx_lock_spin(&((vlapic)->timer_mtx))

sys/amd64/vmm/io/vlapic.c

711

vlapic_callout_reset(struct vlapic *vlapic, sbintime_t t)

sys/amd64/vmm/io/vlapic.c

713

callout_reset_sbt_curcpu(&vlapic->callout, t, 0,

sys/amd64/vmm/io/vlapic.c

714

vlapic_callout_handler, vlapic, 0);

sys/amd64/vmm/io/vlapic.c

72

#define VLAPIC_TIMER_UNLOCK(vlapic) mtx_unlock_spin(&((vlapic)->timer_mtx))

sys/amd64/vmm/io/vlapic.c

720

struct vlapic *vlapic;

sys/amd64/vmm/io/vlapic.c

724

vlapic = arg;

sys/amd64/vmm/io/vlapic.c

726

VLAPIC_TIMER_LOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

727

if (callout_pending(&vlapic->callout)) /* callout was reset */

sys/amd64/vmm/io/vlapic.c

73

#define VLAPIC_TIMER_LOCKED(vlapic) mtx_owned(&((vlapic)->timer_mtx))

sys/amd64/vmm/io/vlapic.c

730

if (!callout_active(&vlapic->callout)) /* callout was stopped */

sys/amd64/vmm/io/vlapic.c

733

callout_deactivate(&vlapic->callout);

sys/amd64/vmm/io/vlapic.c

735

vlapic_fire_timer(vlapic);

sys/amd64/vmm/io/vlapic.c

737

if (vlapic_periodic_timer(vlapic)) {

sys/amd64/vmm/io/vlapic.c

739

KASSERT(bintime_cmp(&btnow, &vlapic->timer_fire_bt, >=),

sys/amd64/vmm/io/vlapic.c

741

btnow.sec, btnow.frac, vlapic->timer_fire_bt.sec,

sys/amd64/vmm/io/vlapic.c

742

vlapic->timer_fire_bt.frac));

sys/amd64/vmm/io/vlapic.c

749

bintime_sub(&bt, &vlapic->timer_fire_bt);

sys/amd64/vmm/io/vlapic.c

751

rem_sbt = bttosbt(vlapic->timer_period_bt);

sys/amd64/vmm/io/vlapic.c

752

if (bintime_cmp(&bt, &vlapic->timer_period_bt, <)) {

sys/amd64/vmm/io/vlapic.c

764

vlapic->timer_fire_bt = btnow;

sys/amd64/vmm/io/vlapic.c

765

VLAPIC_CTR2(vlapic, "vlapic timer lagging by %lu "

sys/amd64/vmm/io/vlapic.c

768

bttosbt(vlapic->timer_period_bt) / SBT_1US);

sys/amd64/vmm/io/vlapic.c

771

bintime_add(&vlapic->timer_fire_bt, &vlapic->timer_period_bt);

sys/amd64/vmm/io/vlapic.c

772

vlapic_callout_reset(vlapic, rem_sbt);

sys/amd64/vmm/io/vlapic.c

775

VLAPIC_TIMER_UNLOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

779

vlapic_icrtmr_write_handler(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

785

VLAPIC_TIMER_LOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

787

lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

790

vlapic->timer_period_bt = vlapic->timer_freq_bt;

sys/amd64/vmm/io/vlapic.c

791

bintime_mul(&vlapic->timer_period_bt, icr_timer);

sys/amd64/vmm/io/vlapic.c

794

binuptime(&vlapic->timer_fire_bt);

sys/amd64/vmm/io/vlapic.c

795

bintime_add(&vlapic->timer_fire_bt, &vlapic->timer_period_bt);

sys/amd64/vmm/io/vlapic.c

797

sbt = bttosbt(vlapic->timer_period_bt);

sys/amd64/vmm/io/vlapic.c

798

vlapic_callout_reset(vlapic, sbt);

sys/amd64/vmm/io/vlapic.c

800

callout_stop(&vlapic->callout);

sys/amd64/vmm/io/vlapic.c

802

VLAPIC_TIMER_UNLOCK(vlapic);

sys/amd64/vmm/io/vlapic.c

816

struct vlapic *vlapic;

sys/amd64/vmm/io/vlapic.c

82

static void vlapic_set_error(struct vlapic *, uint32_t, bool);

sys/amd64/vmm/io/vlapic.c

84

static void vlapic_reset(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.c

866

vlapic = vm_lapic(vm_vcpu(vm, vcpuid));

sys/amd64/vmm/io/vlapic.c

867

dfr = vlapic->apic_page->dfr;

sys/amd64/vmm/io/vlapic.c

868

ldr = vlapic->apic_page->ldr;

sys/amd64/vmm/io/vlapic.c

87

vlapic_get_id(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

876

if (x2apic(vlapic)) {

sys/amd64/vmm/io/vlapic.c

891

VLAPIC_CTR1(vlapic, "vlapic has bad logical "

sys/amd64/vmm/io/vlapic.c

90

if (x2apic(vlapic))

sys/amd64/vmm/io/vlapic.c

909

vlapic_set_tpr(struct vlapic *vlapic, uint8_t val)

sys/amd64/vmm/io/vlapic.c

91

return (vlapic->vcpuid);

sys/amd64/vmm/io/vlapic.c

911

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

914

VLAPIC_CTR2(vlapic, "vlapic TPR changed from %#x to %#x",

sys/amd64/vmm/io/vlapic.c

917

vlapic_update_ppr(vlapic);

sys/amd64/vmm/io/vlapic.c

922

vlapic_get_tpr(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

924

struct LAPIC *lapic = vlapic->apic_page;

sys/amd64/vmm/io/vlapic.c

93

return (vlapic->vcpuid << 24);

sys/amd64/vmm/io/vlapic.c

930

vlapic_set_cr8(struct vlapic *vlapic, uint64_t val)

sys/amd64/vmm/io/vlapic.c

935

vm_inject_gp(vlapic->vcpu);

sys/amd64/vmm/io/vlapic.c

940

vlapic_set_tpr(vlapic, tpr);

sys/amd64/vmm/io/vlapic.c

944

vlapic_get_cr8(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.c

948

tpr = vlapic_get_tpr(vlapic);

sys/amd64/vmm/io/vlapic.c

97

x2apic_ldr(struct vlapic *vlapic)

sys/amd64/vmm/io/vlapic.h

101

void vlapic_id_write_handler(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

102

void vlapic_ldr_write_handler(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

103

void vlapic_dfr_write_handler(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

104

void vlapic_svr_write_handler(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

105

void vlapic_esr_write_handler(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

106

int vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu);

sys/amd64/vmm/io/vlapic.h

107

void vlapic_icrtmr_write_handler(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

108

void vlapic_dcr_write_handler(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

109

void vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset);

sys/amd64/vmm/io/vlapic.h

110

void vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val);

sys/amd64/vmm/io/vlapic.h

36

int vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,

sys/amd64/vmm/io/vlapic.h

38

int vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,

sys/amd64/vmm/io/vlapic.h

51

int vlapic_pending_intr(struct vlapic *vlapic, int *vecptr);

sys/amd64/vmm/io/vlapic.h

59

void vlapic_intr_accepted(struct vlapic *vlapic, int vector);

sys/amd64/vmm/io/vlapic.h

64

int vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level);

sys/amd64/vmm/io/vlapic.h

71

void vlapic_post_intr(struct vlapic *vlapic, int hostcpu, int ipinum);

sys/amd64/vmm/io/vlapic.h

73

void vlapic_fire_cmci(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

74

int vlapic_trigger_lvt(struct vlapic *vlapic, int vector);

sys/amd64/vmm/io/vlapic.h

76

void vlapic_sync_tpr(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

78

uint64_t vlapic_get_apicbase(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

79

int vlapic_set_apicbase(struct vlapic *vlapic, uint64_t val);

sys/amd64/vmm/io/vlapic.h

81

bool vlapic_enabled(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

87

void vlapic_reset_tmr(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic.h

94

void vlapic_set_tmr_level(struct vlapic *vlapic, uint32_t dest, bool phys,

sys/amd64/vmm/io/vlapic.h

97

void vlapic_set_cr8(struct vlapic *vlapic, uint64_t val);

sys/amd64/vmm/io/vlapic.h

98

uint64_t vlapic_get_cr8(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic_priv.h

100

uint32_t *irrptr = &(vlapic)->apic_page->irr0; \

sys/amd64/vmm/io/vlapic_priv.h

102

VLAPIC_CTR1((vlapic), msg " irr0 0x%08x", irrptr[0 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

103

VLAPIC_CTR1((vlapic), msg " irr1 0x%08x", irrptr[1 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

104

VLAPIC_CTR1((vlapic), msg " irr2 0x%08x", irrptr[2 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

105

VLAPIC_CTR1((vlapic), msg " irr3 0x%08x", irrptr[3 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

106

VLAPIC_CTR1((vlapic), msg " irr4 0x%08x", irrptr[4 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

107

VLAPIC_CTR1((vlapic), msg " irr5 0x%08x", irrptr[5 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

108

VLAPIC_CTR1((vlapic), msg " irr6 0x%08x", irrptr[6 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

109

VLAPIC_CTR1((vlapic), msg " irr7 0x%08x", irrptr[7 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

112

#define VLAPIC_CTR_ISR(vlapic, msg) \

sys/amd64/vmm/io/vlapic_priv.h

114

uint32_t *isrptr = &(vlapic)->apic_page->isr0; \

sys/amd64/vmm/io/vlapic_priv.h

116

VLAPIC_CTR1((vlapic), msg " isr0 0x%08x", isrptr[0 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

117

VLAPIC_CTR1((vlapic), msg " isr1 0x%08x", isrptr[1 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

118

VLAPIC_CTR1((vlapic), msg " isr2 0x%08x", isrptr[2 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

119

VLAPIC_CTR1((vlapic), msg " isr3 0x%08x", isrptr[3 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

120

VLAPIC_CTR1((vlapic), msg " isr4 0x%08x", isrptr[4 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

121

VLAPIC_CTR1((vlapic), msg " isr5 0x%08x", isrptr[5 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

122

VLAPIC_CTR1((vlapic), msg " isr6 0x%08x", isrptr[6 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

123

VLAPIC_CTR1((vlapic), msg " isr7 0x%08x", isrptr[7 << 2]); \

sys/amd64/vmm/io/vlapic_priv.h

134

struct vlapic;

sys/amd64/vmm/io/vlapic_priv.h

137

int (*set_intr_ready)(struct vlapic *vlapic, int vector, bool level);

sys/amd64/vmm/io/vlapic_priv.h

138

int (*pending_intr)(struct vlapic *vlapic, int *vecptr);

sys/amd64/vmm/io/vlapic_priv.h

139

void (*intr_accepted)(struct vlapic *vlapic, int vector);

sys/amd64/vmm/io/vlapic_priv.h

140

void (*post_intr)(struct vlapic *vlapic, int hostcpu);

sys/amd64/vmm/io/vlapic_priv.h

141

void (*set_tmr)(struct vlapic *vlapic, int vector, bool level);

sys/amd64/vmm/io/vlapic_priv.h

142

void (*enable_x2apic_mode)(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic_priv.h

183

void vlapic_init(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic_priv.h

184

void vlapic_cleanup(struct vlapic *vlapic);

sys/amd64/vmm/io/vlapic_priv.h

86

#define VLAPIC_CTR0(vlapic, format) \

sys/amd64/vmm/io/vlapic_priv.h

87

VCPU_CTR0((vlapic)->vm, (vlapic)->vcpuid, format)

sys/amd64/vmm/io/vlapic_priv.h

89

#define VLAPIC_CTR1(vlapic, format, p1) \

sys/amd64/vmm/io/vlapic_priv.h

90

VCPU_CTR1((vlapic)->vm, (vlapic)->vcpuid, format, p1)

sys/amd64/vmm/io/vlapic_priv.h

92

#define VLAPIC_CTR2(vlapic, format, p1, p2) \

sys/amd64/vmm/io/vlapic_priv.h

93

VCPU_CTR2((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2)

sys/amd64/vmm/io/vlapic_priv.h

95

#define VLAPIC_CTR3(vlapic, format, p1, p2, p3) \

sys/amd64/vmm/io/vlapic_priv.h

96

VCPU_CTR3((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2, p3)

sys/amd64/vmm/io/vlapic_priv.h

98

#define VLAPIC_CTR_IRR(vlapic, msg) \

sys/amd64/vmm/vmm.c

149

DEFINE_VMMOPS_IFUNC(struct vlapic *, vlapic_init, (void *vcpui))

sys/amd64/vmm/vmm.c

150

DEFINE_VMMOPS_IFUNC(void, vlapic_cleanup, (struct vlapic *vlapic))

sys/amd64/vmm/vmm.c

1598

struct vlapic *

sys/amd64/vmm/vmm.c

1601

return (vcpu->vlapic);

sys/amd64/vmm/vmm.c

1717

vlapic_post_intr(vcpu->vlapic, vcpu->hostcpu, vmm_ipinum);

sys/amd64/vmm/vmm.c

210

vmmops_vlapic_cleanup(vcpu->vlapic);

sys/amd64/vmm/vmm.c

245

vcpu->vlapic = vmmops_vlapic_init(vcpu->cookie);

sys/amd64/vmm/vmm.c

772

vlapic_pending_intr(vcpu->vlapic, NULL)) {

sys/amd64/vmm/vmm.c

93

struct vlapic;

sys/amd64/vmm/vmm_lapic.c

161

struct vlapic *vlapic;

sys/amd64/vmm/vmm_lapic.c

163

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/vmm_lapic.c

166

*rval = vlapic_get_apicbase(vlapic);

sys/amd64/vmm/vmm_lapic.c

170

error = vlapic_read(vlapic, 0, offset, rval, retu);

sys/amd64/vmm/vmm_lapic.c

181

struct vlapic *vlapic;

sys/amd64/vmm/vmm_lapic.c

183

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/vmm_lapic.c

186

error = vlapic_set_apicbase(vlapic, val);

sys/amd64/vmm/vmm_lapic.c

189

error = vlapic_write(vlapic, 0, offset, val, retu);

sys/amd64/vmm/vmm_lapic.c

201

struct vlapic *vlapic;

sys/amd64/vmm/vmm_lapic.c

212

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/vmm_lapic.c

213

error = vlapic_write(vlapic, 1, off, wval, arg);

sys/amd64/vmm/vmm_lapic.c

223

struct vlapic *vlapic;

sys/amd64/vmm/vmm_lapic.c

236

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/vmm_lapic.c

237

error = vlapic_read(vlapic, 1, off, rval, arg);

sys/amd64/vmm/vmm_lapic.c

54

struct vlapic *vlapic;

sys/amd64/vmm/vmm_lapic.c

63

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/vmm_lapic.c

64

if (vlapic_set_intr_ready(vlapic, vector, level))

sys/amd64/vmm/vmm_lapic.c

72

struct vlapic *vlapic;

sys/amd64/vmm/vmm_lapic.c

80

vlapic = vm_lapic(vm_vcpu(vm, cpu));

sys/amd64/vmm/vmm_lapic.c

81

error = vlapic_trigger_lvt(vlapic, vector);

sys/amd64/vmm/vmm_lapic.c

86

vlapic = vm_lapic(vcpu);

sys/amd64/vmm/vmm_lapic.c

87

error = vlapic_trigger_lvt(vlapic, vector);