Symbol: wrmsr
sys/amd64/amd64/initcpu.c
104
wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) |
sys/amd64/amd64/initcpu.c
118
wrmsr(MSR_NB_CFG1, msr);
sys/amd64/amd64/initcpu.c
132
wrmsr(0xc001102a, msr);
sys/amd64/amd64/initcpu.c
146
wrmsr(MSR_LS_CFG, msr);
sys/amd64/amd64/initcpu.c
156
wrmsr(MSR_DE_CFG, msr);
sys/amd64/amd64/initcpu.c
161
wrmsr(MSR_LS_CFG, msr);
sys/amd64/amd64/initcpu.c
166
wrmsr(0xc0011028, msr);
sys/amd64/amd64/initcpu.c
171
wrmsr(MSR_LS_CFG, msr);
sys/amd64/amd64/initcpu.c
224
wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
sys/amd64/amd64/initcpu.c
237
wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
sys/amd64/amd64/initcpu.c
338
wrmsr(MSR_EFER, msr);
sys/amd64/amd64/initcpu.c
343
wrmsr(MSR_EFER, msr);
sys/amd64/amd64/initcpu.c
361
wrmsr(MSR_TSC_AUX, cpu_auxmsr());
sys/amd64/amd64/machdep.c
1188
wrmsr(MSR_EFER, msr);
sys/amd64/amd64/machdep.c
1189
wrmsr(MSR_LSTAR, pti ? (u_int64_t)IDTVEC(fast_syscall_pti) :
sys/amd64/amd64/machdep.c
1191
wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
sys/amd64/amd64/machdep.c
1194
wrmsr(MSR_STAR, msr);
sys/amd64/amd64/machdep.c
1195
wrmsr(MSR_SF_MASK, PSL_NT | PSL_T | PSL_I | PSL_C | PSL_D | PSL_AC);
sys/amd64/amd64/machdep.c
1401
wrmsr(MSR_FSBASE, 0); /* User value */
sys/amd64/amd64/machdep.c
1402
wrmsr(MSR_GSBASE, (u_int64_t)pc);
sys/amd64/amd64/machdep.c
1403
wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
sys/amd64/amd64/mp_machdep.c
276
wrmsr(MSR_FSBASE, 0); /* User value */
sys/amd64/amd64/mp_machdep.c
277
wrmsr(MSR_GSBASE, (uint64_t)pc);
sys/amd64/amd64/mp_machdep.c
278
wrmsr(MSR_KGSBASE, 0); /* User value */
sys/amd64/amd64/pmap.c
2205
wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
sys/amd64/amd64/pmap.c
2219
wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
sys/amd64/amd64/pmap.c
2314
wrmsr(MSR_PAT, pat_msr);
sys/amd64/amd64/trap.c
1175
wrmsr(MSR_IA32_FLUSH_CMD, IA32_FLUSH_CMD_L1D);
sys/amd64/linux32/linux32_sysvec.c
588
wrmsr(MSR_FSBASE, 0);
sys/amd64/linux32/linux32_sysvec.c
589
wrmsr(MSR_KGSBASE, 0); /* User value while we're in the kernel */
sys/amd64/pt/pt.c
233
wrmsr(MSR_IA32_XSS, xss | XFEATURE_ENABLED_PT);
sys/amd64/pt/pt.c
244
wrmsr(MSR_IA32_XSS, xss);
sys/amd64/pt/pt.c
265
wrmsr(MSR_IA32_RTIT_STATUS, 0);
sys/amd64/pt/pt.c
777
wrmsr(MSR_IA_GLOBAL_STATUS_RESET, reg);
sys/amd64/vmm/amd/svm.c
159
wrmsr(MSR_EFER, efer);
sys/amd64/vmm/amd/svm.c
2082
wrmsr(MSR_DEBUGCTLMSR, 0);
sys/amd64/vmm/amd/svm.c
2117
wrmsr(MSR_DEBUGCTLMSR, gctx->host_debugctl);
sys/amd64/vmm/amd/svm.c
219
wrmsr(MSR_EFER, efer);
sys/amd64/vmm/amd/svm.c
221
wrmsr(MSR_VM_HSAVE_PA, vtophys(&hsave[curcpu * PAGE_SIZE]));
sys/amd64/vmm/amd/svm_msr.c
100
wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]);
sys/amd64/vmm/amd/svm_msr.c
101
wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]);
sys/amd64/vmm/amd/svm_msr.c
102
wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]);
sys/amd64/vmm/amd/svm_msr.c
103
wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]);
sys/amd64/vmm/intel/vmx.c
246
SDT_PROBE_DEFINE5(vmm, vmx, exit, wrmsr,
sys/amd64/vmm/intel/vmx.c
2561
SDT_PROBE5(vmm, vmx, exit, wrmsr, vmx, vmexit, vcpuid, ecx,
sys/amd64/vmm/intel/vmx.c
2960
wrmsr(MSR_DEBUGCTLMSR, 0);
sys/amd64/vmm/intel/vmx.c
3007
wrmsr(MSR_DEBUGCTLMSR, vmxctx->host_debugctl);
sys/amd64/vmm/intel/vmx.c
640
wrmsr(MSR_IA32_FEATURE_CONTROL,
sys/amd64/vmm/intel/vmx_msr.c
347
wrmsr(MSR_LSTAR, vcpu->guest_msrs[IDX_MSR_LSTAR]);
sys/amd64/vmm/intel/vmx_msr.c
348
wrmsr(MSR_CSTAR, vcpu->guest_msrs[IDX_MSR_CSTAR]);
sys/amd64/vmm/intel/vmx_msr.c
349
wrmsr(MSR_STAR, vcpu->guest_msrs[IDX_MSR_STAR]);
sys/amd64/vmm/intel/vmx_msr.c
350
wrmsr(MSR_SF_MASK, vcpu->guest_msrs[IDX_MSR_SF_MASK]);
sys/amd64/vmm/intel/vmx_msr.c
351
wrmsr(MSR_KGSBASE, vcpu->guest_msrs[IDX_MSR_KGSBASE]);
sys/amd64/vmm/intel/vmx_msr.c
361
wrmsr(MSR_TSC_AUX, guest_tsc_aux);
sys/amd64/vmm/intel/vmx_msr.c
376
wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]);
sys/amd64/vmm/intel/vmx_msr.c
377
wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]);
sys/amd64/vmm/intel/vmx_msr.c
378
wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]);
sys/amd64/vmm/intel/vmx_msr.c
379
wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]);
sys/amd64/vmm/intel/vmx_msr.c
398
wrmsr(MSR_TSC_AUX, host_aux);
sys/dev/agp/agp_nvidia.c
407
wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
sys/dev/agp/agp_nvidia.c
408
wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
sys/dev/agp/agp_nvidia.c
412
wrmsr(SYSCFG, sys);
sys/dev/glxiic/glxiic.c
1002
wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map);
sys/dev/glxsb/glxsb.c
294
wrmsr(SB_GLD_MSR_CTRL, msr);
sys/dev/hwpmc/hwpmc_amd.c
251
wrmsr(pd->pm_perfctr, v);
sys/dev/hwpmc/hwpmc_amd.c
472
wrmsr(pd->pm_evsel, config);
sys/dev/hwpmc/hwpmc_amd.c
501
wrmsr(pd->pm_evsel, config);
sys/dev/hwpmc/hwpmc_amd.c
592
wrmsr(evsel, config & ~AMD_PMC_ENABLE);
sys/dev/hwpmc/hwpmc_amd.c
593
wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
sys/dev/hwpmc/hwpmc_amd.c
598
wrmsr(evsel, config);
sys/dev/hwpmc/hwpmc_core.c
1039
wrmsr(IAP_EVSEL0 + ri, pm->pm_md.pm_iap.pm_iap_evsel);
sys/dev/hwpmc/hwpmc_core.c
1040
wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v);
sys/dev/hwpmc/hwpmc_core.c
1045
wrmsr(IAP_EVSEL0 + ri, pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN);
sys/dev/hwpmc/hwpmc_core.c
1086
wrmsr(IA_GLOBAL_CTRL, 0);
sys/dev/hwpmc/hwpmc_core.c
1114
wrmsr(IAF_CTR0 + n, v);
sys/dev/hwpmc/hwpmc_core.c
1144
wrmsr(core_iap_wroffset + IAP_PMC0 + n, v);
sys/dev/hwpmc/hwpmc_core.c
1159
wrmsr(IA_GLOBAL_OVF_CTRL, intrstatus);
sys/dev/hwpmc/hwpmc_core.c
1161
wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
sys/dev/hwpmc/hwpmc_core.c
1165
wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
sys/dev/hwpmc/hwpmc_core.c
1167
wrmsr(IA_GLOBAL_OVF_CTRL, intrstatus);
sys/dev/hwpmc/hwpmc_core.c
153
wrmsr(MSR_DEBUGCTLMSR, rdmsr(MSR_DEBUGCTLMSR) | 0x1000);
sys/dev/hwpmc/hwpmc_core.c
185
wrmsr(IAP_EVSEL0 + n, 0);
sys/dev/hwpmc/hwpmc_core.c
188
wrmsr(IAF_CTRL, 0);
sys/dev/hwpmc/hwpmc_core.c
430
wrmsr(IAF_CTRL, cc->pc_iafctrl);
sys/dev/hwpmc/hwpmc_core.c
433
wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
sys/dev/hwpmc/hwpmc_core.c
457
wrmsr(IAF_CTRL, cc->pc_iafctrl);
sys/dev/hwpmc/hwpmc_core.c
484
wrmsr(IAF_CTRL, cc->pc_iafctrl & ~(IAF_MASK << (ri * 4)));
sys/dev/hwpmc/hwpmc_core.c
486
wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
sys/dev/hwpmc/hwpmc_core.c
489
wrmsr(IAF_CTRL, cc->pc_iafctrl);
sys/dev/hwpmc/hwpmc_core.c
901
wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
sys/dev/hwpmc/hwpmc_core.c
904
wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
sys/dev/hwpmc/hwpmc_core.c
910
wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
sys/dev/hwpmc/hwpmc_core.c
914
wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
sys/dev/hwpmc/hwpmc_core.c
931
wrmsr(IAP_EVSEL0 + ri, 0);
sys/dev/hwpmc/hwpmc_core.c
960
wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v);
sys/dev/hwpmc/hwpmc_ibs.c
239
wrmsr(IBS_FETCH_CTL, 0);
sys/dev/hwpmc/hwpmc_ibs.c
241
wrmsr(IBS_FETCH_CTL, config);
sys/dev/hwpmc/hwpmc_ibs.c
244
wrmsr(IBS_OP_CTL, 0);
sys/dev/hwpmc/hwpmc_ibs.c
246
wrmsr(IBS_OP_CTL, config);
sys/dev/hwpmc/hwpmc_ibs.c
287
wrmsr(IBS_FETCH_CTL, config & ~IBS_FETCH_CTL_MAXCNTMASK);
sys/dev/hwpmc/hwpmc_ibs.c
290
wrmsr(IBS_FETCH_CTL, config);
sys/dev/hwpmc/hwpmc_ibs.c
293
wrmsr(IBS_OP_CTL, config & ~IBS_OP_CTL_MAXCNTMASK);
sys/dev/hwpmc/hwpmc_ibs.c
296
wrmsr(IBS_OP_CTL, config);
sys/dev/hwpmc/hwpmc_ibs.c
305
wrmsr(IBS_FETCH_CTL, 0);
sys/dev/hwpmc/hwpmc_ibs.c
308
wrmsr(IBS_OP_CTL, 0);
sys/dev/hwpmc/hwpmc_ibs.c
346
wrmsr(IBS_FETCH_CTL, pm->pm_md.pm_ibs.ibs_ctl | IBS_FETCH_CTL_ENABLE);
sys/dev/hwpmc/hwpmc_ibs.c
374
wrmsr(IBS_OP_CTL, pm->pm_md.pm_ibs.ibs_ctl | IBS_OP_CTL_ENABLE);
sys/dev/hwpmc/hwpmc_ibs.c
523
wrmsr(IBS_FETCH_CTL, 0);
sys/dev/hwpmc/hwpmc_ibs.c
524
wrmsr(IBS_OP_CTL, 0);
sys/dev/hwpmc/hwpmc_uncore.c
150
wrmsr(SELECTSEL(uncore_cputype) + n, 0);
sys/dev/hwpmc/hwpmc_uncore.c
152
wrmsr(UCF_CTRL, 0);
sys/dev/hwpmc/hwpmc_uncore.c
315
wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
sys/dev/hwpmc/hwpmc_uncore.c
318
wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
sys/dev/hwpmc/hwpmc_uncore.c
347
wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
sys/dev/hwpmc/hwpmc_uncore.c
373
wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */
sys/dev/hwpmc/hwpmc_uncore.c
374
wrmsr(UCF_CTR0 + ri, v);
sys/dev/hwpmc/hwpmc_uncore.c
375
wrmsr(UCF_CTRL, cc->pc_ucfctrl);
sys/dev/hwpmc/hwpmc_uncore.c
633
wrmsr(SELECTSEL(uncore_cputype) + ri, evsel);
sys/dev/hwpmc/hwpmc_uncore.c
636
wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
sys/dev/hwpmc/hwpmc_uncore.c
653
wrmsr(SELECTSEL(uncore_cputype) + ri, 0);
sys/dev/hwpmc/hwpmc_uncore.c
680
wrmsr(UCP_PMC0 + ri, v);
sys/dev/hyperv/vmbus/amd64/hyperv_machdep.c
221
wrmsr(MSR_HV_REFERENCE_TSC, val);
sys/dev/hyperv/vmbus/vmbus_et.c
104
wrmsr(MSR_HV_STIMER0_COUNT, current);
sys/dev/hyperv/vmbus/vmbus_et.c
163
wrmsr(MSR_HV_STIMER0_COUNT, 0);
sys/dev/hyperv/vmbus/vmbus_et.c
170
wrmsr(MSR_HV_STIMER0_CONFIG,
sys/dev/hyperv/vmbus/x86/hyperv_machdep.h
35
#define WRMSR(msr, val) wrmsr(msr, val)
sys/dev/hyperv/vmbus/x86/hyperv_x86.c
126
wrmsr(MSR_HV_HYPERCALL, hc);
sys/dev/hyperv/vmbus/x86/hyperv_x86.c
147
wrmsr(MSR_HV_HYPERCALL, (hc & MSR_HV_HYPERCALL_RSVD_MASK));
sys/dev/hyperv/vmbus/x86/vmbus_x86.c
109
wrmsr(MSR_HV_EOM, 0);
sys/dev/kvm_clock/kvm_clock.c
106
wrmsr(sc->msr_tc, vtophys(&(sc->timeinfos)[curcpu]) | 1);
sys/dev/kvm_clock/kvm_clock.c
87
wrmsr(sc->msr_wc, vtophys(&sc->wc));
sys/i386/i386/geode.c
229
wrmsr(0x51400029, m);
sys/i386/i386/initcpu.c
100
wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
sys/i386/i386/initcpu.c
103
wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
sys/i386/i386/initcpu.c
105
wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
sys/i386/i386/initcpu.c
107
wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
sys/i386/i386/initcpu.c
415
wrmsr(0x0107, fcr);
sys/i386/i386/initcpu.c
499
wrmsr(MSR_APICBASE, apicbase);
sys/i386/i386/initcpu.c
516
wrmsr(MSR_APICBASE, apicbase);
sys/i386/i386/initcpu.c
552
wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
sys/i386/i386/initcpu.c
594
wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
sys/i386/i386/initcpu.c
609
wrmsr(0x1107, rdmsr(0x1107) | fcr);
sys/i386/i386/initcpu.c
621
wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
sys/i386/i386/initcpu.c
691
wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
sys/i386/i386/initcpu.c
735
wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
sys/i386/i386/initcpu.c
767
wrmsr(MSR_EFER, msr);
sys/i386/i386/initcpu.c
771
wrmsr(MSR_TSC_AUX, cpu_auxmsr());
sys/i386/i386/initcpu.c
824
wrmsr(0x83, msr & !(0x10));
sys/i386/i386/initcpu.c
841
wrmsr(0x86, 0x0ff00f0);
sys/i386/i386/initcpu.c
843
wrmsr(0x85, msr);
sys/i386/i386/initcpu.c
846
wrmsr(0x83, msr|0x10); /* enable write allocate */
sys/i386/i386/initcpu.c
873
wrmsr(0x0000000e, (u_int64_t)0x0008);
sys/i386/i386/initcpu.c
896
wrmsr(0x0c0000082, whcr);
sys/i386/i386/initcpu.c
923
wrmsr(0x0000000e, (u_int64_t)0x0008);
sys/i386/i386/initcpu.c
946
wrmsr(0x0c0000082, whcr);
sys/i386/i386/initcpu.c
98
wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
sys/i386/i386/k6_mem.c
168
wrmsr(UWCCR, reg);
sys/i386/i386/longrun.c
147
wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
sys/i386/i386/longrun.c
152
wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
sys/i386/i386/perfmon.c
137
wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
sys/i386/i386/perfmon.c
181
wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
sys/i386/i386/perfmon.c
232
wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
sys/i386/i386/perfmon.c
250
wrmsr(msr_ctl[pmc], 0);
sys/i386/i386/perfmon.c
252
wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
sys/i386/i386/perfmon.c
286
wrmsr(msr_ctl[0], newval);
sys/i386/i386/pmap.c
864
wrmsr(MSR_PAT, pat_msr);
sys/x86/cpufreq/est.c
1254
wrmsr(MSR_PERF_CTL, msr);
sys/x86/cpufreq/est.c
975
wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
sys/x86/cpufreq/p4tcc.c
287
wrmsr(MSR_THERM_CONTROL, msr);
sys/x86/cpufreq/powernow.c
147
wrmsr(MSR_AMDK7_FIDVID_CTL, \
sys/x86/cpufreq/powernow.c
295
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
sys/x86/cpufreq/powernow.c
297
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_VIDC);
sys/x86/cpufreq/powernow.c
299
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_VIDC);
sys/x86/cpufreq/powernow.c
301
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
sys/x86/x86/cpu_machdep.c
187
wrmsr(a->msr, v);
sys/x86/x86/cpu_machdep.c
194
wrmsr(a->msr, v);
sys/x86/x86/cpu_machdep.c
197
wrmsr(a->msr, a->arg1);
sys/x86/x86/cpu_machdep.c
397
wrmsr(MSR_IA32_SPEC_CTRL, v & ~(IA32_SPEC_CTRL_IBRS |
sys/x86/x86/cpu_machdep.c
412
wrmsr(MSR_IA32_SPEC_CTRL, v);
sys/x86/x86/cpu_machdep.c
796
wrmsr(MSR_AMDK8_IPM, msr & ~(AMDK8_SMIONCMPHALT |
sys/x86/x86/identcpu.c
1536
wrmsr(MSR_IA32_MISC_ENABLE, msr);
sys/x86/x86/identcpu.c
1553
wrmsr(MSR_EXTFEATURES, msr);
sys/x86/x86/local_apic.c
1554
wrmsr(MSR_TSC_DEADLINE, la->la_timer_period + rdtsc());
sys/x86/x86/local_apic.c
1563
wrmsr(MSR_TSC_DEADLINE, 0);
sys/x86/x86/local_apic.c
373
wrmsr(MSR_APIC_000 + reg, val);
sys/x86/x86/local_apic.c
384
wrmsr(MSR_APIC_000 + reg, val);
sys/x86/x86/local_apic.c
407
wrmsr(MSR_APIC_000 + LAPIC_ICR_LO, v);
sys/x86/x86/local_apic.c
422
wrmsr(MSR_APIC_000 + LAPIC_ICR_LO, vlo);
sys/x86/x86/local_apic.c
433
wrmsr(MSR_APIC_000 + LAPIC_SELF_IPI, vector);
sys/x86/x86/local_apic.c
444
wrmsr(MSR_APICBASE, apic_base);
sys/x86/x86/mca.c
1025
wrmsr(MSR_MC_CTL2(bank), ctl);
sys/x86/x86/mca.c
1050
wrmsr(mca_msr_ops.misc(bank), misc);
sys/x86/x86/mca.c
1410
wrmsr(MSR_MC_CTL2(i), ctl);
sys/x86/x86/mca.c
1421
wrmsr(MSR_MC_CTL2(i), ctl);
sys/x86/x86/mca.c
1428
wrmsr(MSR_MC_CTL2(i), ctl);
sys/x86/x86/mca.c
1459
wrmsr(MSR_MC_CTL2(i), ctl);
sys/x86/x86/mca.c
1487
wrmsr(mca_msr_ops.misc(bank), misc);
sys/x86/x86/mca.c
1591
wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);
sys/x86/x86/mca.c
1606
wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5));
sys/x86/x86/mca.c
1620
wrmsr(MSR_MCG_EXT_CTL, rdmsr(MSR_MCG_EXT_CTL) | 1);
sys/x86/x86/mca.c
1650
wrmsr(mca_msr_ops.ctl(i), ctl);
sys/x86/x86/mca.c
1667
wrmsr(mca_msr_ops.status(i), 0);
sys/x86/x86/mca.c
1753
wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP);
sys/x86/x86/mca.c
865
wrmsr(mca_msr_ops.status(bank), 0);
sys/x86/x86/ucode.c
145
wrmsr(MSR_BIOS_UPDT_TRIG, (uint64_t)(uintptr_t)data);
sys/x86/x86/ucode.c
148
wrmsr(MSR_BIOS_SIGN, 0);
sys/x86/x86/ucode.c
277
wrmsr(MSR_K8_UCODE_UPDATE, (uint64_t)(uintptr_t)data);
sys/x86/x86/x86_mem.c
343
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
sys/x86/x86/x86_mem.c
356
wrmsr(msr, msrv);
sys/x86/x86/x86_mem.c
368
wrmsr(msr, msrv);
sys/x86/x86/x86_mem.c
380
wrmsr(msr, msrv);
sys/x86/x86/x86_mem.c
396
wrmsr(msr, msrv);
sys/x86/x86/x86_mem.c
405
wrmsr(msr + 1, msrv);
sys/x86/x86/x86_mem.c
413
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
sys/x86/x86/x86_mem.c
697
wrmsr(MSR_MTRRdefType, mtrrdef);
sys/x86/xen/hvm.c
298
wrmsr(regs[1], early_init_vtop(&hypercall_page));