wrmsr_safe
int wrmsr_safe(u_int msr, uint64_t newval);
ret = wrmsr_safe(data->msr, data->data);
ret = wrmsr_safe(data->msr, reg | data->data);
ret = wrmsr_safe(data->msr, reg & ~data->data);
d->ret = wrmsr_safe(MSR_K8_UCODE_UPDATE, (uintptr_t)d->ptr);
wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr));
int wrmsr_safe(u_int msr, uint64_t newval);
error = wrmsr_safe(MSR_AMD_CPPC_REQUEST, new_req);
error = wrmsr_safe(MSR_AMD_CPPC_ENABLE, 1);
error = wrmsr_safe(MSR_AMD_CPPC_REQUEST, data->request);
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST_PKG, sc->req);
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST, sc->req);
ret = wrmsr_safe(MSR_IA32_ENERGY_PERF_BIAS,
ret = wrmsr_safe(MSR_IA32_PM_ENABLE, 1);
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST, sc->req |
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST, sc->req);
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST_PKG, sc->req);
ret = wrmsr_safe(MSR_IA32_PM_ENABLE, 1);
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST, sc->req |
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST, sc->req);
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST_PKG, sc->req);
ret = wrmsr_safe(MSR_IA32_ENERGY_PERF_BIAS,
error = wrmsr_safe(a->msr, v);
error = wrmsr_safe(a->msr, v);
error = wrmsr_safe(a->msr, a->arg1);
wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uint64_t)(uintptr_t)data);
wrmsr_safe(MSR_K8_UCODE_UPDATE, (uint64_t)(uintptr_t)data);