sys/arm/freescale/vybrid/vf_uart.c

159

uart_setreg(bas, UART_D, c);

sys/arm/freescale/vybrid/vf_uart.c

212

uart_setreg(bas, UART_MODEM, 0x00);

sys/arm/freescale/vybrid/vf_uart.c

220

uart_setreg(bas, UART_C2, 0x00);

sys/arm/freescale/vybrid/vf_uart.c

222

uart_setreg(bas, UART_C1, 0x00);

sys/arm/freescale/vybrid/vf_uart.c

230

uart_setreg(bas, UART_BDH, reg);

sys/arm/freescale/vybrid/vf_uart.c

233

uart_setreg(bas, UART_BDL, reg);

sys/arm/freescale/vybrid/vf_uart.c

238

uart_setreg(bas, UART_C4, reg);

sys/arm/freescale/vybrid/vf_uart.c

242

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

308

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

379

uart_setreg(bas, UART_S2, usr2);

sys/arm/freescale/vybrid/vf_uart.c

384

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

394

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

461

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

481

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

499

uart_setreg(bas, UART_D, sc->sc_txbuf[i] & 0xff);

sys/arm/freescale/vybrid/vf_uart.c

508

uart_setreg(bas, UART_C2, reg);

sys/arm/nvidia/tegra_uart.c

101

uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);

sys/arm/nvidia/tegra_uart.c

106

uart_setreg(bas, REG_FCR, 0);

sys/arm/nvidia/tegra_uart.c

121

uart_setreg(bas, REG_FCR, ns8250->fcr);

sys/arm/nvidia/tegra_uart.c

122

uart_setreg(bas, REG_IER, ns8250->ier);

sys/arm/nvidia/tegra_uart.c

82

uart_setreg(bas, REG_IER, ns8250->ier);

sys/arm64/apple/exynos_uart.c

180

uart_setreg(bas, SSCOM_ULCON, ulcon);

sys/arm64/apple/exynos_uart.c

185

uart_setreg(bas, SSCOM_UBRDIV, brd);

sys/arm64/apple/exynos_uart.c

230

uart_setreg(bas, SSCOM_UTRSTAT, 0);

sys/arm64/apple/exynos_uart.c

232

uart_setreg(bas, SSCOM_UCON, 0);

sys/arm64/apple/exynos_uart.c

233

uart_setreg(bas, SSCOM_UFCON,

sys/arm64/apple/exynos_uart.c

243

uart_setreg(bas, SSCOM_UCON, uart_getreg(bas, SSCOM_UCON) |

sys/arm64/apple/exynos_uart.c

247

uart_setreg(bas, SSCOM_UCON, uart_getreg(bas, SSCOM_UCON) |

sys/arm64/apple/exynos_uart.c

249

uart_setreg(bas, SSCOM_UMCON, UMCON_RTS);

sys/arm64/apple/exynos_uart.c

288

uart_setreg(bas, SSCOM_UTXH, c);

sys/arm64/apple/exynos_uart.c

413

uart_setreg(&sc->sc_bas, SSCOM_UTXH, sc->sc_txbuf[i]);

sys/dev/uart/uart_dev_msm.c

121

uart_setreg(bas, UART_DM_MR2, ulcon);

sys/dev/uart/uart_dev_msm.c

162

uart_setreg(bas, UART_DM_MR1, 0x0);

sys/dev/uart/uart_dev_msm.c

165

uart_setreg(bas, UART_DM_IMR, 0);

sys/dev/uart/uart_dev_msm.c

172

uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE);

sys/dev/uart/uart_dev_msm.c

175

uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE);

sys/dev/uart/uart_dev_msm.c

181

uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB);

sys/dev/uart/uart_dev_msm.c

184

uart_setreg(bas, UART_DM_IRDA, 0x0);

sys/dev/uart/uart_dev_msm.c

191

uart_setreg(bas, UART_DM_HCR, 0x0);

sys/dev/uart/uart_dev_msm.c

201

uart_setreg(bas, UART_DM_DMEN, UART_DM_DMEN_RX_SC_ENABLE);

sys/dev/uart/uart_dev_msm.c

204

uart_setreg(bas, UART_DM_CR, UART_DM_CR_RX_ENABLE);

sys/dev/uart/uart_dev_msm.c

205

uart_setreg(bas, UART_DM_CR, UART_DM_CR_TX_ENABLE);

sys/dev/uart/uart_dev_msm.c

240

uart_setreg(bas, UART_DM_NO_CHARS_FOR_TX, 1);

sys/dev/uart/uart_dev_msm.c

273

uart_setreg(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);

sys/dev/uart/uart_dev_msm.c

349

uart_setreg(bas, UART_DM_IMR, u->ier);

sys/dev/uart/uart_dev_mvebu.c

176

uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST |

sys/dev/uart/uart_dev_mvebu.c

206

uart_setreg(bas, UART_CCR, ccr | divisor);

sys/dev/uart/uart_dev_mvebu.c

214

uart_setreg(bas, UART_CTRL, ctrl);

sys/dev/uart/uart_dev_mvebu.c

228

uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) &

sys/dev/uart/uart_dev_mvebu.c

240

uart_setreg(bas, UART_TSH, c & 0xff);

sys/dev/uart/uart_dev_mvebu.c

338

uart_setreg(bas, UART_CTRL, ctrl);

sys/dev/uart/uart_dev_mvebu.c

365

uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST);

sys/dev/uart/uart_dev_mvebu.c

370

uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST);

sys/dev/uart/uart_dev_mvebu.c

381

uart_setreg(bas, UART_CTRL, ctrl);

sys/dev/uart/uart_dev_mvebu.c

412

uart_setreg(bas, UART_CTRL, ctrl);

sys/dev/uart/uart_dev_mvebu.c

445

uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT);

sys/dev/uart/uart_dev_mvebu.c

557

uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);

sys/dev/uart/uart_dev_mvebu.c

561

uart_setreg(bas, UART_TSH, sc->sc_txbuf[i] & 0xff);

sys/dev/uart/uart_dev_mvebu.c

569

uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT);

sys/dev/uart/uart_dev_mvebu.c

590

uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);

sys/dev/uart/uart_dev_mvebu.c

605

uart_setreg(bas, UART_CTRL, ctrl | msc->intrm);

sys/dev/uart/uart_dev_ns8250.c

1006

uart_setreg(bas, REG_IER, ier);

sys/dev/uart/uart_dev_ns8250.c

1007

uart_setreg(bas, REG_MCR, mcr);

sys/dev/uart/uart_dev_ns8250.c

1008

uart_setreg(bas, REG_FCR, 0);

sys/dev/uart/uart_dev_ns8250.c

1017

uart_setreg(bas, REG_LCR, uart_getreg(bas, REG_LCR));

sys/dev/uart/uart_dev_ns8250.c

1025

uart_setreg(bas, REG_MCR, mcr);

sys/dev/uart/uart_dev_ns8250.c

1145

uart_setreg(bas, REG_MCR, ns8250->mcr);

sys/dev/uart/uart_dev_ns8250.c

1163

uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);

sys/dev/uart/uart_dev_ns8250.c

1168

uart_setreg(bas, REG_IER, ns8250->ier);

sys/dev/uart/uart_dev_ns8250.c

1205

uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);

sys/dev/uart/uart_dev_ns8250.c

1220

uart_setreg(bas, REG_IER, ns8250->ier);

sys/dev/uart/uart_dev_ns8250.c

177

uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);

sys/dev/uart/uart_dev_ns8250.c

181

uart_setreg(bas, REG_LCR, lcr);

sys/dev/uart/uart_dev_ns8250.c

293

uart_setreg(bas, REG_FCR, fcr);

sys/dev/uart/uart_dev_ns8250.c

343

uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);

sys/dev/uart/uart_dev_ns8250.c

345

uart_setreg(bas, REG_DLL, divisor & 0xff);

sys/dev/uart/uart_dev_ns8250.c

346

uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);

sys/dev/uart/uart_dev_ns8250.c

351

uart_setreg(bas, REG_LCR, lcr);

sys/dev/uart/uart_dev_ns8250.c

410

uart_setreg(bas, REG_IER, ier);

sys/dev/uart/uart_dev_ns8250.c

438

uart_setreg(bas, REG_FCR, 0);

sys/dev/uart/uart_dev_ns8250.c

442

uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);

sys/dev/uart/uart_dev_ns8250.c

453

uart_setreg(bas, REG_MCR, MCR_IE);

sys/dev/uart/uart_dev_ns8250.c

467

uart_setreg(bas, REG_DATA, c);

sys/dev/uart/uart_dev_ns8250.c

661

uart_setreg(bas, REG_FCR, ns8250->fcr);

sys/dev/uart/uart_dev_ns8250.c

674

uart_setreg(bas, REG_IER, ns8250->ier);

sys/dev/uart/uart_dev_ns8250.c

702

uart_setreg(bas, REG_IER, ier);

sys/dev/uart/uart_dev_ns8250.c

719

uart_setreg(bas, REG_FCR, ns8250->fcr);

sys/dev/uart/uart_dev_ns8250.c

782

uart_setreg(bas, REG_LCR, lcr);

sys/dev/uart/uart_dev_ns8250.c

788

uart_setreg(bas, REG_LCR, 0xbf);

sys/dev/uart/uart_dev_ns8250.c

795

uart_setreg(bas, REG_EFR, efr);

sys/dev/uart/uart_dev_ns8250.c

797

uart_setreg(bas, REG_LCR, lcr);

sys/dev/uart/uart_dev_ns8250.c

803

uart_setreg(bas, REG_LCR, 0xbf);

sys/dev/uart/uart_dev_ns8250.c

810

uart_setreg(bas, REG_EFR, efr);

sys/dev/uart/uart_dev_ns8250.c

812

uart_setreg(bas, REG_LCR, lcr);

sys/dev/uart/uart_dev_ns8250.c

866

uart_setreg(bas, REG_IER, ns8250->ier);

sys/dev/uart/uart_dev_ns8250.c

945

uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);

sys/dev/uart/uart_dev_ns8250.c

953

uart_setreg(bas, REG_FCR, FCR_ENABLE);

sys/dev/uart/uart_dev_ns8250.c

960

uart_setreg(bas, REG_MCR, mcr);

sys/dev/uart/uart_dev_ns8250.c

967

uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);

sys/dev/uart/uart_dev_ns8250.c

976

uart_setreg(bas, REG_MCR, mcr);

sys/dev/uart/uart_dev_ns8250.c

977

uart_setreg(bas, REG_FCR, 0);

sys/dev/uart/uart_dev_ns8250.c

990

uart_setreg(bas, REG_DATA, 0);

sys/dev/uart/uart_dev_ti8250.c

82

uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_DISABLE);

sys/dev/uart/uart_dev_ti8250.c

83

uart_setreg(&sc->sc_bas, SYSCC_REG, SYSCC_SOFTRESET);

sys/dev/uart/uart_dev_ti8250.c

86

uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_UART);

sys/dev/uart/uart_dev_z8530.c

232

uart_setreg(bas, REG_DATA, c);

sys/dev/uart/uart_dev_z8530.c

457

uart_setreg(bas, REG_CTRL, CR_RSTTXI);

sys/dev/uart/uart_dev_z8530.c

466

uart_setreg(bas, REG_CTRL, CR_RSTXSI);

sys/dev/uart/uart_dev_z8530.c

479

uart_setreg(bas, REG_CTRL, CR_RSTERR);

sys/dev/uart/uart_dev_z8530.c

486

uart_setreg(bas, REG_CTRL, CR_RSTIUS);

sys/dev/uart/uart_dev_z8530.c

554

uart_setreg(bas, REG_CTRL, CR_RSTERR);

sys/dev/uart/uart_dev_z8530.c

565

uart_setreg(bas, REG_CTRL, CR_RSTERR);

sys/dev/uart/uart_dev_z8530.c

57

uart_setreg(bas, REG_CTRL, reg);

sys/dev/uart/uart_dev_z8530.c

59

uart_setreg(bas, REG_CTRL, val);

sys/dev/uart/uart_dev_z8530.c

620

uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);

sys/dev/uart/uart_dev_z8530.c

66

uart_setreg(bas, REG_CTRL, reg);

sys/riscv/sifive/sifive_uart.c

102

uart_setreg(bas, SFUART_IRQ_ENABLE, 0);

sys/riscv/sifive/sifive_uart.c

108

uart_setreg(bas, SFUART_RXCTRL, reg);

sys/riscv/sifive/sifive_uart.c

117

uart_setreg(bas, SFUART_TXCTRL, reg);

sys/riscv/sifive/sifive_uart.c

131

uart_setreg(bas, SFUART_TXDATA, c);

sys/riscv/sifive/sifive_uart.c

222

uart_setreg(bas, SFUART_RXCTRL, reg);

sys/riscv/sifive/sifive_uart.c

226

uart_setreg(bas, SFUART_TXCTRL, reg);

sys/riscv/sifive/sifive_uart.c

229

uart_setreg(bas, SFUART_IRQ_ENABLE, SFUART_IRQ_ENABLE_RXWM);

sys/riscv/sifive/sifive_uart.c

244

uart_setreg(bas, SFUART_RXCTRL, 0);

sys/riscv/sifive/sifive_uart.c

245

uart_setreg(bas, SFUART_TXCTRL, 0);

sys/riscv/sifive/sifive_uart.c

248

uart_setreg(bas, SFUART_IRQ_ENABLE, 0);

sys/riscv/sifive/sifive_uart.c

376

uart_setreg(bas, SFUART_IRQ_ENABLE, ie);

sys/riscv/sifive/sifive_uart.c

416

uart_setreg(bas, SFUART_DIV, reg);

sys/riscv/sifive/sifive_uart.c

461

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);

sys/riscv/sifive/sifive_uart.c

484

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);

sys/riscv/sifive/sifive_uart.c

500

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);