uart_getreg - FreeBSD

sys/arm/freescale/vybrid/vf_uart.c

156

while (!(uart_getreg(bas, UART_S1) & UART_S1_TDRE))

sys/arm/freescale/vybrid/vf_uart.c

167

usr1 = uart_getreg(bas, UART_S1);

sys/arm/freescale/vybrid/vf_uart.c

182

while (!(uart_getreg(bas, UART_S1) & UART_S1_RDRF))

sys/arm/freescale/vybrid/vf_uart.c

185

c = uart_getreg(bas, UART_D);

sys/arm/freescale/vybrid/vf_uart.c

218

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

227

reg = uart_getreg(bas, UART_BDH);

sys/arm/freescale/vybrid/vf_uart.c

235

reg = uart_getreg(bas, UART_C4);

sys/arm/freescale/vybrid/vf_uart.c

240

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

302

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

374

usr1 = uart_getreg(bas, UART_S1);

sys/arm/freescale/vybrid/vf_uart.c

375

usr2 = uart_getreg(bas, UART_S2);

sys/arm/freescale/vybrid/vf_uart.c

376

(void)uart_getreg(bas, UART_SFIFO);

sys/arm/freescale/vybrid/vf_uart.c

382

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

392

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

447

while (uart_getreg(bas, UART_S1) & UART_S1_RDRF) {

sys/arm/freescale/vybrid/vf_uart.c

454

c = uart_getreg(bas, UART_D);

sys/arm/freescale/vybrid/vf_uart.c

459

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

479

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

506

reg = uart_getreg(bas, UART_C2);

sys/arm/nvidia/tegra_uart.c

100

ier = uart_getreg(bas, REG_IER);

sys/arm/nvidia/tegra_uart.c

103

while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)

sys/arm/nvidia/tegra_uart.c

80

ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;

sys/arm64/apple/exynos_uart.c

243

uart_setreg(bas, SSCOM_UCON, uart_getreg(bas, SSCOM_UCON) |

sys/arm64/apple/exynos_uart.c

247

uart_setreg(bas, SSCOM_UCON, uart_getreg(bas, SSCOM_UCON) |

sys/arm64/apple/exynos_uart.c

328

return (uart_getreg(bas, SSCOM_URXH));

sys/arm64/apple/exynos_uart.c

454

uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH));

sys/dev/uart/uart_dev_msm.c

233

if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) {

sys/dev/uart/uart_dev_msm.c

234

while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0

sys/dev/uart/uart_dev_msm.c

243

while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0)

sys/dev/uart/uart_dev_msm.c

255

return ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) ==

sys/dev/uart/uart_dev_msm.c

267

while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) !=

sys/dev/uart/uart_dev_msm.c

272

if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN)

sys/dev/uart/uart_dev_msm.c

276

c = uart_getreg(bas, UART_DM_RF(0));

sys/dev/uart/uart_dev_msm.c

412

while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) {

sys/dev/uart/uart_dev_msm.c

420

c = uart_getreg(bas, UART_DM_RF(0));

sys/dev/uart/uart_dev_mvebu.c

175

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

203

ccr = uart_getreg(bas, UART_CCR);

sys/dev/uart/uart_dev_mvebu.c

228

uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) &

sys/dev/uart/uart_dev_mvebu.c

238

while (uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_FULL)

sys/dev/uart/uart_dev_mvebu.c

246

if (uart_getreg(bas, UART_STAT) & STAT_RX_RDY)

sys/dev/uart/uart_dev_mvebu.c

257

while (!(uart_getreg(bas, UART_STAT) & STAT_RX_RDY))

sys/dev/uart/uart_dev_mvebu.c

260

c = uart_getreg(bas, UART_RBR) & 0xff;

sys/dev/uart/uart_dev_mvebu.c

331

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

361

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

407

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

417

divisor = uart_getreg(bas, UART_CCR) & CCR_BAUDRATE_DIV;

sys/dev/uart/uart_dev_mvebu.c

439

ipend = uart_getreg(bas, UART_STAT);

sys/dev/uart/uart_dev_mvebu.c

440

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

449

while(!(uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_EMPT))

sys/dev/uart/uart_dev_mvebu.c

504

while (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) {

sys/dev/uart/uart_dev_mvebu.c

510

xc = uart_getreg(bas, UART_RBR);

sys/dev/uart/uart_dev_mvebu.c

531

if (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) {

sys/dev/uart/uart_dev_mvebu.c

556

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

588

ctrl = uart_getreg(bas, UART_CTRL);

sys/dev/uart/uart_dev_mvebu.c

604

ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK;

sys/dev/uart/uart_dev_ns8250.c

1000

while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&

sys/dev/uart/uart_dev_ns8250.c

1005

ier = uart_getreg(bas, REG_IER) & 0xe0;

sys/dev/uart/uart_dev_ns8250.c

1017

uart_setreg(bas, REG_LCR, uart_getreg(bas, REG_LCR));

sys/dev/uart/uart_dev_ns8250.c

1086

lsr = uart_getreg(bas, REG_LSR);

sys/dev/uart/uart_dev_ns8250.c

1103

xc = uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_ns8250.c

1109

lsr = uart_getreg(bas, REG_LSR);

sys/dev/uart/uart_dev_ns8250.c

1113

(void)uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_ns8250.c

1115

lsr = uart_getreg(bas, REG_LSR);

sys/dev/uart/uart_dev_ns8250.c

1160

while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)

sys/dev/uart/uart_dev_ns8250.c

1185

if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) !=

sys/dev/uart/uart_dev_ns8250.c

1204

ier = uart_getreg(bas, REG_IER);

sys/dev/uart/uart_dev_ns8250.c

154

iir = uart_getreg(bas, REG_IIR);

sys/dev/uart/uart_dev_ns8250.c

158

lsr = uart_getreg(bas, REG_LSR);

sys/dev/uart/uart_dev_ns8250.c

160

(void)uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_ns8250.c

162

(void)uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_ns8250.c

164

(void)uart_getreg(bas, REG_MSR);

sys/dev/uart/uart_dev_ns8250.c

166

iir = uart_getreg(bas, REG_IIR);

sys/dev/uart/uart_dev_ns8250.c

176

lcr = uart_getreg(bas, REG_LCR);

sys/dev/uart/uart_dev_ns8250.c

179

divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);

sys/dev/uart/uart_dev_ns8250.c

238

while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)

sys/dev/uart/uart_dev_ns8250.c

260

while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {

sys/dev/uart/uart_dev_ns8250.c

262

(void)uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_ns8250.c

264

} while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit);

sys/dev/uart/uart_dev_ns8250.c

303

lsr = uart_getreg(bas, REG_LSR);

sys/dev/uart/uart_dev_ns8250.c

381

val = uart_getreg(bas, REG_IIR);

sys/dev/uart/uart_dev_ns8250.c

390

val = uart_getreg(bas, REG_MCR);

sys/dev/uart/uart_dev_ns8250.c

409

ier = uart_getreg(bas, REG_IER) & 0xe0;

sys/dev/uart/uart_dev_ns8250.c

464

while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)

sys/dev/uart/uart_dev_ns8250.c

475

return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);

sys/dev/uart/uart_dev_ns8250.c

485

while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {

sys/dev/uart/uart_dev_ns8250.c

491

c = uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_ns8250.c

628

ns8250->mcr = uart_getreg(bas, REG_MCR);

sys/dev/uart/uart_dev_ns8250.c

672

ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;

sys/dev/uart/uart_dev_ns8250.c

701

ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;

sys/dev/uart/uart_dev_ns8250.c

749

msr = uart_getreg(&sc->sc_bas, REG_MSR);

sys/dev/uart/uart_dev_ns8250.c

777

lcr = uart_getreg(bas, REG_LCR);

sys/dev/uart/uart_dev_ns8250.c

786

lcr = uart_getreg(bas, REG_LCR);

sys/dev/uart/uart_dev_ns8250.c

790

efr = uart_getreg(bas, REG_EFR);

sys/dev/uart/uart_dev_ns8250.c

801

lcr = uart_getreg(bas, REG_LCR);

sys/dev/uart/uart_dev_ns8250.c

805

efr = uart_getreg(bas, REG_EFR);

sys/dev/uart/uart_dev_ns8250.c

842

iir = uart_getreg(bas, REG_IIR);

sys/dev/uart/uart_dev_ns8250.c

845

(void)uart_getreg(bas, DW_REG_USR);

sys/dev/uart/uart_dev_ns8250.c

855

lsr = uart_getreg(bas, REG_LSR);

sys/dev/uart/uart_dev_ns8250.c

899

while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&

sys/dev/uart/uart_dev_ns8250.c

955

if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {

sys/dev/uart/uart_dev_ti8250.c

84

while (uart_getreg(&sc->sc_bas, SYSS_REG) & SYSS_STATUS_RESETDONE)

sys/dev/uart/uart_dev_z8530.c

230

while (!(uart_getreg(bas, REG_CTRL) & BES_TXE))

sys/dev/uart/uart_dev_z8530.c

240

return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0);

sys/dev/uart/uart_dev_z8530.c

250

while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) {

sys/dev/uart/uart_dev_z8530.c

256

c = uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_z8530.c

543

xc = uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_z8530.c

561

(void)uart_getreg(bas, REG_DATA);

sys/dev/uart/uart_dev_z8530.c

68

return (uart_getreg(bas, REG_CTRL));

sys/riscv/sifive/sifive_uart.c

127

while ((uart_getreg(bas, SFUART_TXDATA) & SFUART_TXDATA_FULL)

sys/riscv/sifive/sifive_uart.c

144

return ((uart_getreg(bas, SFUART_IRQ_PENDING) &

sys/riscv/sifive/sifive_uart.c

155

while (((c = uart_getreg(bas, SFUART_RXDATA)) &

sys/riscv/sifive/sifive_uart.c

266

reg = uart_getreg(bas, SFUART_TXDATA);

sys/riscv/sifive/sifive_uart.c

272

reg = uart_getreg(bas, SFUART_RXDATA);

sys/riscv/sifive/sifive_uart.c

337

reg = uart_getreg(bas, SFUART_DIV);

sys/riscv/sifive/sifive_uart.c

367

reg = uart_getreg(bas, SFUART_IRQ_PENDING);

sys/riscv/sifive/sifive_uart.c

368

ie = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

404

reg = uart_getreg(bas, SFUART_TXCTRL);

sys/riscv/sifive/sifive_uart.c

432

reg = uart_getreg(bas, SFUART_RXDATA);

sys/riscv/sifive/sifive_uart.c

441

reg = uart_getreg(bas, SFUART_RXDATA);

sys/riscv/sifive/sifive_uart.c

459

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

482

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

498

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);