ure_ocp_reg_read
reg = ure_ocp_reg_read(sc, 0xa5d4);
static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
ure_ocp_reg_read(sc, 0xa468) & ~0x0a);
ure_ocp_reg_read(sc, 0xa466) & ~0x01);
val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR);
ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS);
if (ure_ocp_reg_read(sc, 0xe000) & 0x0100)
val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
(void)ure_ocp_reg_read(sc,
bmsr = ure_ocp_reg_read(sc,
(void)ure_ocp_reg_read(sc,
bmsr = ure_ocp_reg_read(sc,