tx_state
read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg);
tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg);
read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
read_tx_state_one(sc, i, &tx_state[i]);
check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
rx_pause = tx_state[i].rx_pause;
tx_frames = tx_state[i].tx_frames;
read_tx_state_one(sc, i, &tx_state[i]); /* update */
rx_pause != tx_state[i].rx_pause &&
tx_frames == tx_state[i].tx_frames) {
struct port_tx_state tx_state[MAX_NPORTS];
read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */
check_tx_state(adap, &tx_state[0]);
struct ecp_tx_state tx_state;
ql_get_tx_state(qla_host_t *ha, qla_drvr_state_tx_t *tx_state)
tx_state->base_p_addr = ha->hw.tx_cntxt[i].tx_ring_paddr;
tx_state->cons_p_addr = ha->hw.tx_cntxt[i].tx_cons_paddr;
tx_state->tx_prod_reg = ha->hw.tx_cntxt[i].tx_prod_reg;
tx_state->tx_cntxt_id = ha->hw.tx_cntxt[i].tx_cntxt_id;
tx_state->txr_free = ha->hw.tx_cntxt[i].txr_free;
tx_state->txr_next = ha->hw.tx_cntxt[i].txr_next;
tx_state->txr_comp = ha->hw.tx_cntxt[i].txr_comp;
tx_state++;