tx_queue_size
uint32_t tx_queue_size = ENA_DEFAULT_RING_SIZE;
tx_queue_size = clamp_val(tx_queue_size, ENA_MIN_RING_SIZE,
tx_queue_size = 1 << (flsl(tx_queue_size) - 1);
ctx->tx_queue_size = tx_queue_size;
adapter->requested_tx_ring_size = calc_queue_ctx.tx_queue_size;
uint32_t tx_queue_size;
queue_len = sc->tx_queue_size;
count += sc->tx_queue_size;
ENETC_TXQ_WR4(sc, i, ENETC_TBLENR, sc->tx_queue_size);
unsigned int tx_queue_size;
unsigned int tx_queue_size;
tx_queue_size = apc->tx_queue_size;
MANA_IDX_NEXT(next_to_complete, tx_queue_size);
for (i = 0; i < apc->tx_queue_size; i++) {
txq_size = apc->tx_queue_size * 32;
cq_size = apc->tx_queue_size * COMP_ENTRY_SIZE;
txq->tx_buf_info = malloc(apc->tx_queue_size *
txq->txq_br = buf_ring_alloc(4 * apc->tx_queue_size,
apc->tx_queue_size = mana_get_tx_queue_size(port_idx,
unsigned int tx_queue_size = apc->tx_queue_size;
next_to_use = MANA_IDX_NEXT(next_to_use, tx_queue_size);
"tx_queue_size", CTLFLAG_RD, &apc->tx_queue_size, 0,
m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \
m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \
order_base_2(priv->params_ethtool.tx_queue_size);
priv->params_ethtool.tx_queue_size =
priv->params_ethtool.tx_queue_size = 1 << priv->params.log_sq_size;
uint64_t max = priv->params_ethtool.tx_queue_size /
case MLX5_PARAM_OFFSET(tx_queue_size):
if (priv->params_ethtool.tx_queue_size <
priv->params_ethtool.tx_queue_size =
} else if (priv->params_ethtool.tx_queue_size >
priv->params_ethtool.tx_queue_size =
case MLX5E_RL_PARAMS_INDEX(tx_queue_size):
uint64_t max = rl->param.tx_queue_size /
uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size);
uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size);
param->tx_queue_size = (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);