tr_wr
tr_wr(tr, treg, regno | trw, 4);
tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4);
tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4);
tr_wr(tr, reg, i, 4);
tr_wr(tr, TR_REG_CIR, i, 4);
tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4);
tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4);
tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4);
tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4);
tr_wr(tr, TR_REG_SBCTRL, i, 1);
tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2);
tr_wr(tr, TR_REG_DMAR15, 0, 1);
tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1);
tr_wr(tr, TR_REG_DMAR0, ch->buffer->buf_addr, 4);
tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4);
tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1);
tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1);
tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4);
tr_wr(tr, SPA_REG_GPIO, 0, 4);
tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4);
tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4);
tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4);
tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4);