ti_sdma_write_4
ti_sdma_write_4(sc, DMA4_IRQENABLE_L(i), 0x00000000);
ti_sdma_write_4(sc, DMA4_OCP_SYSCONFIG, 0x0002);
ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
ti_sdma_write_4(sc, addr, 0x00000000);
ti_sdma_write_4(sc, DMA4_CICR(ch), 0);
ti_sdma_write_4(sc, DMA4_CCR(ch), 0);
ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
ti_sdma_write_4(sc, addr, 0x00000000);
ti_sdma_write_4(sc, DMA4_CICR(ch), 0x0000);
ti_sdma_write_4(sc, DMA4_IRQENABLE_L(j), irq_enable);
ti_sdma_write_4(sc, DMA4_CICR(ch), flags);
ti_sdma_write_4(sc, DMA4_IRQENABLE_L(0), irq_enable);
ti_sdma_write_4(sc, DMA4_CSDP(ch),
ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);
ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);
ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);
ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
ti_sdma_write_4(sc, DMA4_CCR(ch), channel->reg_ccr);
ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);
ti_sdma_write_4(sc, DMA4_CSF(ch), 0x0001);
ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);
ti_sdma_write_4(sc, DMA4_CDF(ch), 0x0001);
ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);
ti_sdma_write_4(sc, DMA4_CSDP(ch),
ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);
ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);
ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);
ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
ti_sdma_write_4(sc, DMA4_CCR(ch),
ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);
ti_sdma_write_4(sc, DMA4_CSF(ch), pktsize);
ti_sdma_write_4(sc, DMA4_CDF(ch), pktsize);
ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);
ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);
ti_sdma_write_4(sc, DMA4_CICR(ch), 0);
ti_sdma_write_4(sc, DMA4_CCR(ch), 0);
ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));