DMTIMER_WRITE4
DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
DMTIMER_WRITE4(sc, DMT_TLDR, 0xFFFFFFFF - reload_count);
DMTIMER_WRITE4(sc, DMT_TCRR, 0xFFFFFFFF - initial_count);
DMTIMER_WRITE4(sc, DMT_IRQENABLE_SET, DMT_IRQ_OVF);
DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
DMTIMER_WRITE4(sc, DMT_IRQENABLE_CLR, DMT_IRQ_OVF);
DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
DMTIMER_WRITE4(sc, DMT_TSICR, DMT_TSICR_RESET);
DMTIMER_WRITE4(sc, DMT_TLDR, 0);
DMTIMER_WRITE4(sc, DMT_TCRR, 0);
DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_TCAR);
DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
DMTIMER_WRITE4(sc, DMT_TSICR, DMT_TSICR_RESET);
DMTIMER_WRITE4(sc, DMT_TLDR, 0);
DMTIMER_WRITE4(sc, DMT_TCRR, 0);
DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);