superio_read
val = superio_read(sc->dev, ioreg);
return (superio_read(sc->dev, ioreg));
group_drive = superio_read(sc->dev, ioreg);
group_drive = superio_read(sc->dev, ioreg);
group_io = superio_read(sc->dev, ioreg);
superio_read(dev, 0xf6)
if (superio_read(dev, 0x73) != val)
val = superio_read(dev, 0x71);
v = superio_read(dev, sc->enable_reg); /* FIXME enable_reg not used by nctgpio(4). */
uint8_t superio_read(device_t dev, uint8_t reg);
sc->reg_1 = superio_read(sc->dev, sc->ctl_reg);
sc->reg_timeout = superio_read(sc->dev, sc->time_reg);
sc->reg_2 = superio_read(sc->dev, sc->csr_reg);
sc->reg_2 = superio_read(sc->dev, sc->csr_reg);
sc->reg_1 = superio_read(sc->dev, sc->ctl_reg);
sc->reg_2 = superio_read(sc->dev, sc->csr_reg);
t = superio_read(dev, 0x2B) & ~0x10;
t = superio_read(dev, 0x29) & ~0x60;
t = superio_read(dev, 0x2b) & ~0x04;
t = (superio_read(dev, 0x2B) & ~0x08) | 0x04;
t = superio_read(dev, 0x2D) & ~0x01; /* PIN77 -> WDT0# */
t = superio_read(dev, sc->ctl_reg);
t = superio_read(dev, 0x2C) & ~0x80; /* PIN47 -> WDT0# */
t = superio_read(dev, sc->ctl_reg);
sc->reg_1 = superio_read(dev, sc->ctl_reg);
sc->reg_timeout = superio_read(dev, sc->time_reg);
sc->reg_2 = superio_read(dev, sc->csr_reg);