sys/arm/nvidia/tegra124/tegra124_car.c

264

DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 2),

sys/arm/nvidia/tegra124/tegra124_car.c

265

DIV7_1(0, "pllM_out1_div", "pllM_out0", PLLM_OUT, 8),

sys/arm/nvidia/tegra124/tegra124_car.c

266

DIV7_1(0, "pllP_outX0_div", "pllP_out0", PLLP_RESHIFT, 2),

sys/arm/nvidia/tegra124/tegra124_car.c

267

DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8),

sys/arm/nvidia/tegra124/tegra124_car.c

268

DIV7_1(0, "pllP_out2_div", "pllP_out0", PLLP_OUTA, 24),

sys/arm/nvidia/tegra124/tegra124_car.c

269

DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),

sys/arm/nvidia/tegra124/tegra124_car.c

270

DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),

sys/arm/nvidia/tegra124/tegra124_car.c

271

DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24),

sys/arm/nvidia/tegra124/tegra124_car.c

272

DIV7_1(0, "pllA_out1_div", "pllA_out", PLLA_OUT, 8),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

543

DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 8),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

545

DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

547

DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

548

DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

549

DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

552

DIV7_1(0, "pllU_out1_div", "pllU_out0", PLLU_OUTA, 8),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

553

DIV7_1(0, "pllU_out2_div", "pllU_out0", PLLU_OUTA, 24),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

556

DIV7_1(0, "pllREFE_out1_div", "pllREFE", PLLREFE_OUT, 8),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

560

DIV7_1(0, "pllC4_out3_div", "pllC4_out0", PLLC4_OUT, 8),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

562

DIV7_1(0, "pllA_out0_div", "pllA", PLLA_OUT, 8),