t4_tp_pio_read
void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true);
t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true);
t4_tp_pio_read(adap, &v, 1, A_TP_CHANNEL_MAP, true);
t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,
t4_tp_pio_read(padap, sp, reg_offset_range, reg_local_offset, true);
t4_tp_pio_read(padap, sp, reg_offset_range, reg_local_offset, true);
t4_tp_pio_read(padap, sp, reg_offset_range, reg_local_offset, true);
t4_tp_pio_read(padap, sp, reg_offset_range, reg_local_offset, true);
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_TX0 + i),
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_TX0 + i),
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
t4_tp_pio_read(sc, &lo, 1, A_TP_ROCE_RRQ_BASE, false);
t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);