t4_set_reg_field
void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
t4_set_reg_field(adapter, hss_cfg0, F_HSSPDWNPLLB |
t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0);
t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN);
t4_set_reg_field(adap, A_SGE_INT_ENABLE3, mask, val);
t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
t4_set_reg_field(adap, A_PL_INT_ENABLE, F_MAC0 | F_MAC1 | F_MAC2 | F_MAC3, 0);
t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0);
t4_set_reg_field(adap, match_ctl_a, en, enable ? en : 0);
t4_set_reg_field(adap, match_ctl_a, en, 0);
t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U,
t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0);
t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN |
t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE,
t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP,
t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val);
t4_set_reg_field(sc, A_TP_KEEP_IDLE,
t4_set_reg_field(sc, A_TP_KEEP_INTVL,
t4_set_reg_field(sc, A_TP_SHIFT_CNT,
t4_set_reg_field(sc, A_TP_RXT_MIN,
t4_set_reg_field(sc, A_TP_RXT_MAX,
t4_set_reg_field(sc, A_TP_SHIFT_CNT,
t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
t4_set_reg_field(sc, A_MPS_TRC_CFG,
t4_set_reg_field(sc, A_MPS_TRC_CFG,
t4_set_reg_field(sc, A_ULP_RX_TDDP_TAGMASK,