t3_set_reg_field
t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,
t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,
t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,
t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, 0);
t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, gpio);
void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_PRTYEN | F_MBUSEN,
t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_DBGIEN,
t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_TMMODE | F_COMPEN,
t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset,
t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset,
t3_set_reg_field(adapter, A_XGM_INT_ENABLE + mac->offset,
t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + mac->offset,
t3_set_reg_field(adapter, A_XGM_STAT_CTRL + mac->offset,
t3_set_reg_field(adapter,
t3_set_reg_field(adapter,
t3_set_reg_field(adapter, A_TP_OUT_CONFIG,
t3_set_reg_field(adap, A_XGM_INT_ENABLE + mac->offset,
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0);
t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN);
t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3));
t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_FILTEREN, 0);
t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG,
t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
t3_set_reg_field(adap, A_TP_PC_CONFIG,
t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,
t3_set_reg_field(adap, A_TP_PARA_REG3, 0,
t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
t3_set_reg_field(adap, A_TP_PC_CONFIG,
t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0,
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);
t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);
t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0);
t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0,
t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0);
t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE);
t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL,
t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,
t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
t3_set_reg_field(adap, A_PCIE_CFG, 0,
t3_set_reg_field(adapter, A_PCIX_CFG, 0,
t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0,
t3_set_reg_field(adapter, A_PL_RST, 0, F_FATALPERREN);
t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset,
t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset, 0,
t3_set_reg_field(mac->adapter, A_XGM_SERDES_STAT0 + mac->offset,
t3_set_reg_field(mac->adapter, A_XGM_SERDES_STAT1 + mac->offset,
t3_set_reg_field(mac->adapter, A_XGM_SERDES_STAT2 + mac->offset,
t3_set_reg_field(mac->adapter, A_XGM_SERDES_STAT3 + mac->offset,
t3_set_reg_field(mac->adapter, A_XGM_SERDES_STAT0 + mac->offset,
t3_set_reg_field(mac->adapter, A_XGM_SERDES_STAT1 + mac->offset,
t3_set_reg_field(mac->adapter, A_XGM_SERDES_STAT2 + mac->offset,
t3_set_reg_field(mac->adapter, A_XGM_SERDES_STAT3 + mac->offset,
t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0, F_UNDERUNFIX);
t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0,
t3_set_reg_field(adap, A_XGM_RX_CFG + oft, 0, F_COPYPREAMBLE |
t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft,
t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 0);
t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 0);
t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, F_ENFORCEPKT);
t3_set_reg_field(adap, A_XGM_RX_CFG + oft, F_COPYALLFRAMES,
t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx,
t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
t3_set_reg_field(adap, ctrl, clear[i], 0);
t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
t3_set_reg_field(sc, A_XGM_TX_CFG + pi->mac.offset, F_TXPAUSEEN, 0);
t3_set_reg_field(sc, A_XGM_RXFIFO_CFG + pi->mac.offset,
t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP,
t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP,
t3_set_reg_field(sc, A_SG_CONTROL, F_GLOBALENABLE, F_GLOBALENABLE);
t3_set_reg_field(sc, A_SG_CONTROL, F_GLOBALENABLE, 0);
t3_set_reg_field(sc, A_TP_PC_CONFIG2, F_ENABLERXPKTTMSTPRSS,