DMACH_WRITE
DMACH_WRITE(&sc->sc_ndma_channels[index], AWIN_NDMA_CTL_REG, 0);
DMACH_WRITE(&sc->sc_ddma_channels[index], AWIN_DDMA_CTL_REG, 0);
DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
DMACH_WRITE(ch, AWIN_DDMA_PARA_REG,
DMACH_WRITE(ch, AWIN_NDMA_SRC_ADDR_REG, src);
DMACH_WRITE(ch, AWIN_NDMA_DEST_ADDR_REG, dst);
DMACH_WRITE(ch, AWIN_NDMA_BC_REG, nbytes);
DMACH_WRITE(ch, AWIN_DDMA_SRC_START_ADDR_REG, src);
DMACH_WRITE(ch, AWIN_DDMA_DEST_START_ADDR_REG, dst);
DMACH_WRITE(ch, AWIN_DDMA_BC_REG, nbytes);